SATSITY

SATellite-level spatial diverSITY

STATUS | Ongoing
STATUS DATE | 11/08/2025
ACTIVITY CODE | 3A.202
SATSITY

Objectives

Traditionally, satellite communication dedicates separate frequency bands for uplink and downlink. However, in certain frequency bands, the same frequency is allocated for both.

To achieve simultaneous transmit/receive on a single frequency band, this project develops a VHF-to-C-band satellite communication system concept, utilising distinct transmit-only and receive-only satellites for user links. This includes a user terminal and protocols for data and signaling via these separate uplink and downlink satellites. Key to full spectrum use are the constellation architecture, air interface protocol, and satellite spatial diversity.

Challenges

Several challenges must be addressed:

  • Assess the air interface protocol’s properties to verify its support for simultaneous up/down links.
  • Design a constellation of satellites, each solely capable of transmitting or receiving, along with a synchronisation technique.
  • Develop an RF front-end that implements spatial diversity at the satellite level.

Balance the entire system, considering the simplicity of constellation management, synchronization requirements, the effective use of inter-satellite links, networking to manage multiple simultaneous links, and overall solution cost.

System Architecture

Two primary use cases are envisioned: a maritime VHF Data Exchange System (VDES) satellite communication application and a Low Data Rate Mobile Satellite System (LDRMSS) IoT solution. These differ in their air interface protocols and frequency bands. The VDES application adheres to ITU VDE-SAT recommendations and operates in the VHF band. The LDRMSS solution operates in a new proposed satellite L-band (WRC resolution 252).

Multiple constellation architectures are assessed, in particular with and without data-relay links. Low Earth orbit (LEO) satellites are always included, while medium Earth orbit (MEO) and geostationary orbit (GEO) satellites are considered based on a benefit trade-off analysis.

Plan

The project plan foresees a unique phase which includes the following milestones after the kick-off meeting (T0):

  • Use cases consolidation (T0+1M)
  • Requirements Review (T0+4M)
  • Preliminary Design Review (T0+5M)
  • Critical Design Review (T0+7M)
  • Test Readiness Review (T0+11M)
  • Test Review Board (T0+15M and T0+17M)
  • Final Review (T0+18M)

The planned total duration of the project is 18 months.

Current Status

The project has just begun, following the kick-off meeting.

BEACON

W-band Integrated Active Receive Front-End

STATUS | Ongoing
STATUS DATE | 14/07/2025
ACTIVITY CODE | 5C.432
BEACON

Objectives

In this activity, a W-band integrated active receive front-end module at an operating frequency of 81 to 86 GHz was investigated. The module is based on Fraunhofer IAF’s ultra low-noise 50-nm metamorphic High Electron Mobility Transistors (mHEMTs) Monolithic Microwave Integrated Circuits (MMIC) technology. It doubles the channel capacity by separating and amplifying both the Left-Hand Circular Polarization (LHCP) and Right-Hand Circular Polarization (RHCP) components. At the same time, the project targets a significant reduction in noise figure performance as compared to previous W-Band Low Noise Amplifier (LNA) modules.

To that end, this activity covers both the design of novel low-noise amplifiers as well as their seamless integration in a frontend module that features a square or circular waveguide as input and a coaxial output connector for each polarization. One important aspect of the project is the lateral size requirement of less than 3λ for the entire module, which includes all RF components as well as the biasing circuitry. To separate the two incoming polarizations, several novel and ultra-compact polarizer implementations were considered in terms of their size, insertion loss and manufacturability. Furthermore, the project also targets a significant improvement of the noise figure to below 3.5 dB, while maintaining a gain value in excess of 30 dB. Also, the project team investigated ways to implement compact and high-performance out-of-band rejection filters, such that signals below the frequency range of interest are attenuated significantly.

Challenges

The key challenges of this activity include both the investigation of novel ultra-low noise amplifier MMICs and suitable module integration solutions.

More specifically, the MMIC investigation targets an amplifier that simultaneously features high gain and input return loss, an excellent noise figure and compactness.

The module on the other hand must exhibit a maximum footprint of 3λ (10.8 mm) in both dimensions of the antenna. Within this space, a multitude of functions must be realized: this includes the polarizer, waveguide transitions to two individual amplifiers, two coaxial output connectors and associated DC bias circuitry.

System Architecture

The W-band receive-front end consists of a waveguide input that supports LHCP/RHCP modes (square waveguide). The input signal feeds a polarizer, after which the signal is routed to two separate low-noise amplifier MMICs. A transmit rejection filter attenuates unwanted signals from the transmit path. The two amplified signals are then routed to coaxial output connectors. A DC biasing system provides accurate gate and drain voltages for each of the amplifier’s stages.

Plan

In the first work package, an overview of suitable semiconductor technologies and components is compiled. A baseline architecture and a verification plan are developed. Work package 2 entails design and processing of the critical components. In the third work package, a preliminary design baseline is established. WP four contains the development of implementation, test and verification plans. A second iteration of design, manufacturing and assessment of the required elements is allocated in work package 5. This work package also entails assembly and full characterization of the complete module. In WP6, the results are evaluated and a roadmap is laid out for commercialisation.

Current Status

The project has been successfully completed.

STRATIFY

Simulator of Very High Throughput Satellite with Flexible Payload

STATUS | Ongoing
STATUS DATE | 10/06/2025
ACTIVITY CODE | 3A.105
STRATIFY

Objectives

The Project develops and validates end-to-end performance simulators for flexible Very High Throughput Satellites embarking active antennas and digital processors.

Challenges

The simulator assesses VHTS payload performance in the far field with realistic signal excitation, focusing on architectural and functional performance with emphasis on high simulation speed.

System Architecture

High-level architecture of STRATIFY Simulator is based on an Object-Oriented development approach based on the organisation and implementation of module representative of typical VHTS system mainly for the space segment as in following figure:

Simulator Object-Oriented Development Approach

 

 

 

 

 

 


STRATIFY Simulator basic software architecture

The STRATIFY Simulator workflow management is the main tasks of the Orchestrator module and it aims to overcome the sequential approach in the configuration and execution of the modules simulating the sub-systems composing the E2E VHTS System. In this way is possible to take advantage of the opportunity to parallelise some processing common between each module. This orchestrator role is detailed in following figure:

 

STRATIFY Simulator basic software architecture

 

 

 

 

 

 


STRATIFY Simulator modules interoperability

The Orchestrator functionalities are complemented by the data format used for configuring the simulator and for managing the information produced and exchanged by the various modules.

Plan

The contractual milestones implemented in the Project frame execution after the Kick-Off are:

  • Progress Meeting 1 (PM1)
  • Mid Term Review (MTR)
  • Progress Meeting 2 (PM2)
  • Progress Meeting 3 (PM3)
  • Final Review (FR)

Current Status

The Project has been concluded end of 2024.

GRETA

Demonstrator of a ReconfiGurable V-Band FeedeR Link MultibEam AnTenna for High-Capacity GeostationAry Satellites

STATUS | Ongoing
STATUS DATE | 30/04/2025
ACTIVITY CODE | 5B.215
GRETA

Objectives

The objective of the activity is to develop and test a scalable, generic and reconfigurable multibeam receive antenna architecture for feeder links, operating in V-band and supporting high-capacity, geostationary, broadband multimedia missions.

Challenges

The challenge of the project is the replacement of multiple (typically four or more) feeder link reflector antennas by a single antenna.

System Architecture

In order to assess the potential product features, various types of antenna architectures are part of the trade-off:

  1. active phased arrays magnified by reflector(s);
  2. active phased arrays;
  3. discrete lens antennas.

Suitable active components (LNA) identification, Beam-forming networks (BFN) typology, mass, volume, dimensions, complexity, thermal management, operational/ environmental constraints are the subjects to be optimised.

Plan

GRETA contract started on 01.03.2024. Expected project duration is 24 months.

The following project milestones are considered within the overall project development:

  • KoM – Kick-Off Meeting;
  • SRR – System Requirements Review;
  • PDR – Preliminary Design Review;
  • CDR – Detailed Design Review;
  • TRR – Test Readiness Review;
  • TRB – Team Review Board;
  • FR – Final Review.

Current Status

The project’s PDR has been achieved.

PHOTON-MIX

Large-Scale Integrated Silicon Photonic MEMS Switch Matrix

STATUS | Ongoing
STATUS DATE | 16/04/2025
ACTIVITY CODE | 5C.364
PHOTON-MIX

Objectives

The objective of PHOTON-MIX is the development of a high-port-count, low-mass-and-energy-consumption, fast switch matrix for optical communications in the C-band. The enabling technologies to address simultaneously all these requirements are integrated photonics and latching bistable MEMS switches. The former allows to concentrate a great number of optical devices in a cm-sized silicon microchip, thus providing high number of channels and compactness: low size and weight. The latter make it possible to set the state of each of the switch of the matrix either ON or OFF without the need of maintaining a voltage applied constantly to fix this state: this accounts for low power consumption.

Challenges

The key challenges of this project include the demonstration of the MEMS latching mechanism, the development of a reliable microfabrication process flow, the development of a dedicated driving electronics board, and the assembly including all mechanical support structures and electrical and optical interfaces.

System Architecture

The general architecture has been consolidated with some preliminary analysis assessment for the thermos-mechanical and mechanical analysis. The functionality of the bias matrix was successfully demonstrated with some optimisation performed during the switch matrix test. The electronics design offers the required flexibility. Not all verification could be implemented due to project time line and budget. However, the critical aspects of the design have been tested.

Plan

The requirements have been consolidated shortly after Kick-off which enable the launch of LLI procurement and the start of preliminary design activities. Critical design aspects of the preliminary design have been bread boarded and tested. Their results were assessed during the Critical Bread boarding Test Review allowing to carry on with the Demonstration Model (DM) design activities. After finalisation of the MEMs design materialised by the Detailed Design Review, the manufacturing of the DM was released. Testing on the DM was performed following successful TRR, results and associated documentation (product roadmap) were evaluated during the Final Review.

Current Status

The non-volatile MEMS design based on optical switch matrix is available. The fabrication process implemented at EPFL clean room facilities and based on DUV lithography compatible with foundry process has been validated. The non-volatile MEMs switch has been integrated into a modular unit named DM, fully packaged and easy to use. The operational functionality (optical & electrical) of a MEMs switch was fully verified in a lab environment allowing to reach TRL 4.

VISTAM

V band Inter Satellite link solid sTate power Amplifier Module

STATUS | Completed
STATUS DATE | 25/03/2025
ACTIVITY CODE | 5C.381
VISTAM

Objectives

The main objective of this activity is to enable inter-satellite communication link at 5000 km distance and with up to 10 Gbps capacity. In order to achieve the required data rate and link length, the main technical objective is to increase both the bandwidth and the transmitted power. In the first case, a greater bandwidth availability allows the use of wider frequency channels. In the second case, the idea is to allow the use of higher-order modulations, increasing the number of bits per symbol. The overall result derived from the combination of these two approaches allows to reach the target requirements. This PA is able to provide 10W of output power measured at P1dB over the whole 59-71 GHz frequency band ensuring enough power and linearity to enable communication link up to 5000 km with enough linearity to work with highly complex modulated signals. In Fig 1 the whole amplifier, in Fig 2 a single PA module. 

Fig 1
Fig 2

Challenges

This project combines three challenging requirements: high output power at high frequency and over wide bandwidth. GaN/SiC processes are able to provide high output power with sufficient gain at V-band, but the required value of P1dB cannot be achieved with a single device. The high power amplifier combines 8 GaN module in a waveguide structure. To minimize the risks involved with this project two different PA have been designed and manufactured using two different GaN processes from Fraunhofer (0.1µm and 0.15µm gate length), moreover transistor model accuracy and device reliability have been evaluated by University of Ferrara.

System Architecture

Fig 1
Fig 2

The required output power of 10 W at V-band cannot be achieved using a single device with current IC technology. 8 modules are combined to reach the specified power: this is a trade off because increasing the number of elements determines an increased loss and complexity of the output network. The modules number is a consequence of the available power from a single device that is about 33 dBm and the estimated loss of the network that is below 1 dB. Different option were available to realize the combination network: the final selected solution relies on a standard WR15 metallic hollow waveguide branching with three binary levels of H-plane tees. The choice of avoiding balancing resistors guarantees the best insertion loss and lower manufacturing complexity. Furthermore, the planar architecture selected leaves a completely flat surface on the back to ease heat dissipation.

The selected technology for PA is a 0.1 µm GaN/SiC from Fraunhofer, fT/ fMAX are 80 GHz and 200 GHz respectively, with output power up to 2W/mm. Monolithic amplifier is based on a Doherty architecture to have higher P1dB and PAE. In Fig 1 the schematic architecture and in Fig. 2 a 3D model of the amplifier.

Plan

The specification of the front-end HPA (High Power Amplifier) are derived from the ones given by ESA for the full Solid State Power Amplifier. The first activity in the plan is design of the Critical Elements as integrated circuits, combiner/splitter, the transition between MS line and waveguide. Test of these elements follows: any deviation from expected results should be analysed to evaluate its impact on overall performances, eventually the part should be re-designed. When critical elements performances are satisfactory, the HPA can be assembled and fully tested. 

Current Status

Project has been completed with the manufacturing and test of a High Power Amplifier realized using integrated circuits on 0.1µm Ga/SiC process. Measurements demonstrates an output power of 10 W at P1dB over the whole frequency band, the small signal gain is 23 dB.

LFAT

Lead-free assembly technologies for telecom satellite equipment

STATUS | Completed
STATUS DATE | 25/03/2025
ACTIVITY CODE | 5C.411

Objectives

This project covered technology assessment and development of lead free assembly technologies for the space environment. This includes  solder selection, material properties, conditions for higher temperature  reflow, fatigue characteristics, failure modes and adaptation of  assembly techniques used for space hardware.  

Outputs of these activities are made available for the future evolution of  the ECSS-Q-ST-70-61C standard or for dedicated standard for lead free assembly technologies.  

The objective of the activities are to develop techniques and  technologies enabling reliable lead-free assemblies of RF and digital  circuit boards as needed in satcom payloads. An Engineering Model  representing sub-system elements for future constellations and  geostationary commercial applications were manufactured and tested. 

Targeted Improvements were enabling the use of lead-free commercial  EEE components for space application not established today.
 

Challenges

Regulatory pressures, such as RoHS and REACH, necessitate the  adoption of lead-free materials, yet these materials often present  reliability issues, including higher reflow temperatures that can  compromise PCB integrity and increased risks of tin whisker formation.  The selection process for the key candidates during the literature review  was therefore crucial. The lack of established inspection methods for  lead-free solder joints further complicates the process.  

Additionally, achieving the required Technology Readiness Level (TRL)  was key, but further testing and optimization are necessary to reach  higher TRL Levels. 
 

Plan

The project milestones were structured as following: 

  •  MS 01: Technical baseline Selection Review 

    • Phase 1: Finalised Technical Specification 

    • Phase 2: Selected Technical Baseline 

  • MS 02: Technology Review 

    • Phase 3: Verified Detailed Design 

  • MS 03: EM TRR 

    • Phase 4: Implementation and Verification Plan 

  • MS 04: Final Review 

    • Phase 5: Verified Deliverable Items and Compliance  Statement 

    • Phase 6: Technology Assessment and Development Plan  • MS 05: Final Presentation

  • Plan  • MS 05: Final Presentation

Current Status

The project has been completed successfully by providing the  necessary proof that the selected solder candidate has reached the  targeted TRL 5/6. 

KAWA

Ka- to W-band Frequency Converter

STATUS | Ongoing
STATUS DATE | 12/02/2025
ACTIVITY CODE | 5C.437
KAWA

Objectives

The project objectives are to design, manufacture and test a Ka-to W-band frequency up-converter for use as a payload component in high-capacity feeder link systems. European state-of-art MMIC technologies are used for the development of the functional blocks. Superior performances, ideally at the level of the current lower frequency converters, are sought, in order to guarantee the quality of the signal operating in W-band. 

The following tasks are covered by the project:

a) Development of 6 new typologies of MMICs by using the UMS-PH10 foundry process: 1) 27-30 to 71-76 GHz up-converter mixer, employing a sub-harmonic topology; 2) same up-converter mixer also including a by-two frequency multiplier in the LO RF line, in order to enter the LO port at around 10 GHz; 3) Standalone by-two frequency multiplier; 4) 71-76 GHz Voltage Variable Attenuator (VVA); 5) 71-76 GHz Low Level Amplifier (LLA); 6) 71-76 GHz Medium Level Amplifier (MLA). 

b) Development of the hermetic mechanical module housing the above circuits.

c) Development of the hermetic waveguide-to-microstrip transition in W-band.

d) Development of the output W-band waveguide filter 

f) Assembly and Test of the individual functional blocks 

g) Assembly and test of the whole Up-converter unit

Challenges

The main challenge is the design of the MMICs operating in W-band, as the PDK given by the foundry is poorly guaranteed above 60 GHz. In addition, the design of the waveguide-to-microstrip transition is particularly critical from an electrical and technological standpoint, as the size is very small. Also, the waveguide filter is found challenging for manufacturing tolerances and surface roughness. 

System Architecture

The RF line-up of the Frequency Converter is composed by the following functional blocks:

1) Hermetic coax-to-microstrip transition

2) Up-converter mixer MMIC

3) LLA MMIC

4) Microstrip flatness equalizer

5) VVA MMIC

6) LLA MMIC

7) MLA MMIC

8) Microstrip-to-waveguide hermetic transition

9) Waveguide filter 

A conventional board is included in the module performing temperature compensation of the gain and conditioning the supply voltages.

Plan

  • Baseline specification

  • Critical Element design

    Milestone: PDR

  • Critical Elements MFG & test

    Milestone: CDR

  • RF line-up design

    Milestone: DDR

  • RF line-up MFG & test

    Milestone: TRB MMIC

    Milestone: TRB unit

  • Overall evaluation

    Milestone: FR

Current Status

The tasks accomplished up to now are listed below:

  • Baseline specification                       completed 

  • Critical Element design                     completed

    Milestone: PDR                      passed

  • Critical Elements MFG & test           completed

    Milestone: CDR                     passed

  • RF line-up design                             completed 

    Milestone: DDR                     passed

  • RF line-up MFG & test                     in progress

    Milestone: TRB MMIC

    Milestone: TRB unit

  • Overall evaluation

    Milestone: FR

Compact 8kV Class High Voltage Planar Transformer for Electronic Power Conditioning Units

- Compact 8kV Class High Voltage Planar Transformer for Electronic Power Conditioning Units

STATUS | Completed
STATUS DATE | 22/12/2024
ACTIVITY CODE | 5C.382
Compact 8kV Class High Voltage Planar Transformer for Electronic Power Conditioning Units

Objectives

The objective of this activity is to design and develop a high voltage power transformer in planar technology for Electronic Power Conditioning Units (EPC) used to drive travelling wave tubes.

The aim is to develop a novel transformer design solution not existing today in Europe for up to 8kV class of EPCs (with research of margin up to 10kV). 

A transformer engineering model is designed, manufactured and tested in a  representative environment to validate the developed concept for space application.

The main intermediate objectives of this project are: 

  • To establish a detailed requirement specification for the high voltage planar transformer,

  • To define a program (in Excel), based on the build-up in order to compute the tracks size of primary and secondary windings, the leakage inductance, the copper losses of the secondary and primary windings, the core losses, the resonant push-pull losses and rectifier losses,

  • To define thermal and electrical models of the High Voltage Planar technology,

  • To review and de-risk the available technologies and processes available in accordance with the technical requirements defined,

  • To minimise the manufacturing complexity and to ease flexibility during production aiming at a short time to delivery.

Challenges

The main technological challenges are the management of the high electrical fields inside the planar transformer assembly, and the thermal management of the transformer.

The chosen design needs to manage high voltage design rules in PCBs, while at the same time using a more complex build-up than high voltage PCBs currently used.

Thermal design needs to be optimized by using innovating solutions such as optimizing the transformer build-up and improving thermal interfaces with the structure.

System Architecture

Resonant transformer topology working at high frequency.

The Planar transformer technology is based on a high voltage multilayer PCB equipped with its ferrites, thermal conductive material and mechanical fixations.

The secondary side is a single or multiple windings and the primary side is a push-pull type so double windings with a common point.

Plan

The project’s work plan is based on the following methodology:

  1. Based on the state of the art of the Travelling Wave Tube Amplifier, to build the definition of a detailed technical requirement specifications for planar transformer,

  2. To study suitable technologies to achieve a high voltage transformer in planar technology based on a technical trade-off and specific de-risking evaluation activities as High Voltage withstanding aspect,

  3. To study and optimize the electrical and thermal concept of such technological assembly. This step includes detailed calculation and optimization of magnetics tools (including software calculation tools),

  4. After the manufacturing of an Engineering Model (Elegant Bread Board – EBB), to test the High Voltage Planar technology in a realistic EPC environment. The tests sequence includes a Thermal Vacuum test sequence covering GEO mission needs.

Current Status

The main achievements are: 

In the frame of the project Requirements Review (RR):

  • The feasibility study to address the technology to the following TWT tubes has been validated: 150W Ku, 40W Q, 250W Ka, 170W Ka, 300W Ku, 150W C, 75W C, Dual 70W Ka and Compact Dual Ka/Ku TWT’s (80W RF) and for multi-tube constellations market, 

  • The confirmation of implementation feasibility has also been successfully performed ; this study included the following tasks: definition of the preliminary mechanical architecture of the technical solution, planar losses optimization, PCB build-up, preliminary thermal analysis and preliminary electrical fields analysis.

In the frame of the project Technical Design Review (TDR):

  • Several electrical optimizations have been performed including parasitic capacitors computations and leakage inductance distribution,

  • Based on these optimizations, the development of the Planar/PCB build-up has been pushed including thermal and Electrical field analysis,

  • The derisking of the PCB technologies including incoming tests definition, High Voltage ageing behavior (with the definition of a specially dedicated representative test vehicle) and materials performances such as outgassing tests and dielectric strength.

In the frame of the project Preliminary Design Review (PDR): 

  • The definition of the Elegant Breadboard (EBB) ; designed taking into account the challenge to establish a compromise between high voltage insulation properties and sufficient thermal drain capabilities of the HV planar transformer technology studied in the frame of this project.  The demonstrator definition was based on Quadral EPC adapted to the selected TWT’s, i.e. 170W Ka. Detailed calculation and optimization methods for magnetic, electrical and thermal designs have been performed. The design took into account manufacturing and assembly properties in order to minimize the manufacturing complexity and to ease flexibility during production aiming at a short time to delivery. 

In the frame of the project Final Review (FR) : 

  • The planar transformer technology has been exposed to space representative environment. After a first step covering the ground test sequence, a TVAC sequence of 130 thermal cycles has been successfully performed in order to verify the high voltage design and environment effect (including the effect of the local increase of pressure). 10 cold starts at -40°C have also been performed. The test has then been pursued with success with a HV life test at +70°C base plate in order to reach a total test duration of 1500 hours. The test sequence also included thermal characterization under vacuum in order to validate the thermal model related to the evaluated technology.

MMC

- Qualification of MMC Cathodes

STATUS | Ongoing
STATUS DATE | 21/12/2024
ACTIVITY CODE | 5C.321
MMC

Objectives

The achievement of high output power requires a higher energetic electron beam. Technological bricks are more and more challenging, developments for components and materials are getting marginal.

In order to achieve a high electronic flow, with reduced geometrical dimensions, an advanced new electron emission device (MMC) is needed, for a constant high beam current density. This MMC device shall be capable for 5 A/cm² electronic flow through the TWT interaction range. Obviously, the electron ejection has to function constantly for more than the 15 years of the cosmic mission life.

MMC objectives

The MMC emitter is developed from actual MM-type technology, at THALES as a new high current density electronic source. It allows an increase of the current density by lowering the extraction energy for electronic emission.

The new MMC emitter-design is already in use in telecommunication tubes on ground, for high power TWT’s. The non-terrestrial qualification includes a complete batch of MMC-devices, further specific test vehicles and qualification tubes in order to verify the performance of the MMC devices either by accelerated or standard life testing.

Based on a successful qualification, the MMC emitters will serve THALES’ actual and new development projects, where the high emission current density is mandatory.

Challenges

The development of the MMC emitter for 5 A/cm² with 15 years life time can be considered as an evolution out of the well approved and reliable MM-type technology. By lowering the extraction energy for electronic emission, the MM-technology could be systematically improved and verified. Consequently, the MMC device for non-terrestrial application represents the follow-on for the MM-type emitter, including a general process update, while maintaining the reliability aspects of the actual MM–type emitter. In detail, prior to the qualification of the MMC-emitters a further optimisation step for increasing performance and reliability is done by adjusting the manufacturing processes.

System Architecture

The electron beam is generated by the MMC emitting device. By increasing the current density the electron beam becomes more powerful and a higher output power of the TWT can be reached.

High power TWTs are designed such, that they can handle maximum microwave energy, which is automatically correlated to the tube efficiency. So, – under the consideration of a sufficient margin – the following main parameters are adjusted to their physical / material optima: 

  • Temperature

  • Thermo-mechanical stress

  • Thermal gradients

  • Thermal conductivity

  • Electrical field strength

  • Long-term stability

The MMC electron source has to fulfil all of the above criteria, which sometimes need to choose a compromise on materials and processes. Therefore, the selected materials and processes play an outstanding role in this assembly and need to be chosen very carefully.

Plan

The project is divided into three blocks, each finalized by a dedicated milestone.

The first is focused on the process engineering updated and closed by the Preliminary Design Review (PDR/TRR). 

Followed by qualification tests on subassembly level and specific test vehicles, which were finalized by the Critical Design Review (CDR).  Finally, the qualification test on tube level for a 170W Ku-band TWT THL12170C+ was successfully performed and evaluated for the final review.

Current Status

The qualification campaign of the MMC cathode was successfully performed with real improvements for THALES and their customers. With a significant increase of the permissible emission current density up to 5A/cm² future gun designs can be improved with reduced beam compression and therefore improved beam focusing. The customer can expect improved live time behaviour, due to the fact that a chromium-doped MM cathode will ensure improved barium coverage over a long life time. The cathode size can be potentially reduced due to increased current density or kept constant to replace MM cathodes with improved life time behaviour.