KaUF EQM

Ka-Band User Feed Chain EQM

STATUS | Ongoing
STATUS DATE | 20/11/2024
ACTIVITY CODE | 5B.197
KaUF EQM

Objectives

Picture: KaUF EQM (Photo: Airbus)
Picture: KaUF EQM (Photo: Airbus)

Starting point for this activity was the EM design of a combined Tx-Rx Ka band feed chain for user application, developed in a previous program.

This feed chain was further developed and qualified as EQM in a scalable feed cluster. Therefore, beside the RF performance, mass and dimensions were important design drivers. The feed cluster in this program consists of a waveguide panel, designed as beam forming network, carrying 16 horn-polariser assemblies.

Challenges

The design of the Ka band feed chain needs to allow the application in a scalable feed cluster to be used as feed for a multi spot beam antenna. To be able to achieve narrow beam spacing and a compact feed size, the outer diameter of the feed chain was chosen to be 30mm. To achieve a good RF performance with such accommodation constraint, while fulfilling the environmental requirements was the main challenge of this program.

Plan

The project started with the mechanical analysis of the EM feed chain model of the previous program. Design iterations to balance RF performance and mechanical properties followed.

In parallel a waveguide panel with an integrated distribution network was designed. Both designs were performed under the constraint of scalability with respect to the number of feeds in the cluster.

After the detailed design phase all components were manufactured, integrated and tested according to the requirements.

Current Status

The project is completed successfully. 

Additively Manufacturing technology 3D-printed K/Ka Antenna-Feed System with integrated RF, Thermal and Mechanical Functionalities

Additively Manufacturing technology 3D-printed K/Ka Antenna-Feed System with integrated RF, Thermal and Mechanical Functionalities

STATUS | Ongoing
STATUS DATE | 20/11/2024
ACTIVITY CODE | 5B.182 P2
Additively Manufacturing technology 3D-printed K/Ka Antenna-Feed System with integrated RF, Thermal and Mechanical Functionalities

Objectives

Describe in less than 200 words the objectives of the project. 

The satellite communication market is evolving towards medium-volume production of antennas and associated front-ends. Indeed, in GEO applications, complex focal plane arrays of hundreds of antenna-feed chains and BFNs are required to implement Tbps VHTS systems. In LEO and MEO applications, constellations of several hundreds or even thousands of low-cost small satellites are already in operation or will be deployed soon. 

In this framework, additive manufacturing (AM) technologies are being steadily investigated and exploited for the development of RF equipment for satellite communication payloads. Indeed, AM technologies provide several advantages with respect to conventional machining, among which are free-form capability and fit-for-purpose design. These two specific aspects of AM enable the integration of different functionalities in a single monolithic part, thus reducing the number of parts, costs, lead time, and MAIT activities. 

The present project aims at developing through AM a monolithic K/Ka-band dual-circular-polarization antenna-feed system with integrated RF, thermal and mechanical functionalities, intended for GEO High Throughput Satellites.

Challenges

Additive manufacturing technologies offer several advantages in the development of highly integrated RF systems with additional functionalities. However, they also present critical aspects in terms of dimensional accuracy and surface roughness, when RF equipment working at K/Ka bands and in dual-circular polarization are targeted. In this view, one of the main challenges of the present project deal with the RF, mechanical and thermal co-design of the antenna-feed system capable of minimizing the impact of the manufacturing process on the performance. In parallel, challenges apply also on the manufacturing process in order to optimize the production parameters for the intended application.

System Architecture

The K/Ka-band dual-circular-polarization antenna-feed chain developed in the present project consists of a smooth-wall feed-horn and an asymmetrical feeding-network. 

Since a dense focal plane array is considered, the relevant feeding network has to fit within the radiating aperture of the feed horn. Moreover, it was considered the additional goal to minimize the transversal dimension of the feeding network to make feasible its potential application to arrays with smaller lattice steps. Indeed, asymmetric configurations lead to very streamlined geometries, compatible with lattice steps of the focal-plane array in the order of 20 mm, although at some expense in terms of performance (primarily, port-to-port isolation in polarization and XPD). To understand the applicability of these configurations, three different architectures were investigated.

The mechanical design of the EM integrates the adapters towards the standard measurement setup. The design of the thermal circuit integrated in the feeding network was carried out by considering a requirement of thermal dissipation equal to 2.5 W. After a trade-off study and considering the minimum tube dimensions, a Mechanically Pumped Fluid Loop (MPFL) system was selected.

Plan

The project plan consists of one phase, including the following milestones:

  • Requirements Review (RR), focused on requirements at system, antenna and antenna-feed chain level, regarding RF, thermal and mechanical aspects.

  • Mid-Term Review (MTR), focused on the preliminary RF design of the antenna-feed system and bread-boarding of key building blocks.

  • Critical Design Review (CDR), aimed at the consolidation of the RF, thermal and mechanical co-design and additive manufacturing route of the EM.

  • Test Readiness Review (TRR), focused on manufactured EM, test plan, and measurement setups and procedure.

  • Test Review Board (TRB), aimed at the discussion on the comparison among predicted and measured performance of the EM, including RF, thermal and mechanical responses/properties.

  • Final Review (FR), including all the activities carried out during the project and discussion on lessons learnt and follow-on activities.

Current Status

The project was successfully completed. Indeed, the tests performed on the EM confirm the validity of the RF, thermal and mechanical co-design and manufacturing approach and pave the way for a continuation of activities aimed at obtaining a higher TRL.

Feed System Enabling Single Reflector Beam Hopping Antenna for High Throughput Satellites

Feed System Enabling Single Reflector Beam Hopping Antenna for High Throughput Satellites

STATUS | Ongoing
STATUS DATE | 11/11/2024
ACTIVITY CODE | 5B.168
Feed System Enabling Single Reflector Beam Hopping Antenna for High  Throughput Satellites

Objectives

Broadband antennas generating multiple beams within frequency/polarisation  reuse schemes fall into two categories: single feed per beam (SFPB)  requiring at least three antenna apertures, and multiple feed per beam  (MFPB) needing only two apertures but with greater feed system complexity.  In beam hopping or switching applications, the challenges of beam  generation are eased as fewer beams are active simultaneously, enabling  simpler, high-performance antenna designs potentially using just one  aperture. Beam hopping with dedicated pencil beams in high-traffic areas is  commercially valuable, offering flexible, cost-effective traffic management.

The goal was to design an antenna system capable of generating multiple  hopped or switched beams from combined or separate transmit/receive  apertures, reducing the number of apertures and costs by at least half  compared to current solutions. Innovative multibeam antenna solutions  have been investigated for both return and forward links.

Challenges

The “Feed Systems enabling Single Reflector Beam Hopping Antenna For  High Throughput Satellite” study introduces a Multi-Beam Antenna (MBA)  solution designed for flexibility and high-efficiency RF performance across  extensive coverage areas. 

The first major challenge concern the system architectures choices. It  outlines assumptions, constraints, and requirements for versatile V-HTS  missions, considering frequency plans, coverage, and bandwidth flexibility.  Features of TAS Spacebus-Neo and TAS Space Inspire platforms are  discussed, driving the need for a new V-HTS architecture utilizing a TAS  DTP6G based solution. 
 

System Architecture

The system comparison was focused on the following parameters :

  1. System increasing the number of beams in the coverage,

  2. System increasing the frequency band capacity at iso-power  consumed (lower PIRE density), 

  3. Amplification technology (mass, consumption, dissipation,  redundancy management) with Mini-TWT vs SSPA Ka band,

  4. Performances looking at 2 colors FFR (Fractional Frequency  Reuse) versus conventional 4 colors schemes, 

  5. Definition, analyses and interest of MPA 2×2 solutions. 

The separation of the transmission and reception antennas functions in  independent sub-arrays, is naturally conceived on the SPI platform for which  the repeater is specialized with on the one hand a HPA matrix on the East  face and on the other hand, the receive RF chains on the other satellite  side/face.

Plan

This study was divided in five phases:

  1. Beam Hopping antenna Technical Requirements, This phase is devoted to recall the possible architecture of beam hopping  based solutions, to identify the motivations for considering beam hopping  system and finally, to consolidate antenna technical requirements.

  2. Antenna Concept Baseline for Feed System Development, This phase is devoted to identify the preferred beam hopping system and  propose antenna concept and associated technologies. 

  3. Feed System Detailed design & Analysis & EM definition, This phase is devoted to the antenna feed system architecture trade-off,  focused on solutions based on the combined use of HPA matrix and Multi beam antennas in single multibeam antenna (Mono-R) configuration.

  4. Manufacturing and assembly of the EM feed system, This phase was devoted to the manufacturing of the Engineering Model,

  5. RF Test results of the EM feed system This phase was devoted to the tests of the Engineering Model.

Current Status

The activities performed on Feed Systems enabling Single Reflector Beam  Hopping Antenna For High Throughput relative to ARTES AT 5B.168 – contract 4000129443 brings a major step for future Ka flexible Ka V-HTS  system.

A development plan to make the selected antenna/feed system commercially  available has been produced, fixing the TRL at the 7th level, compatible with  a medium/long-term (2025 timescale) for its achievement. An antenna demonstrator showed the high degree of maturity of the solution.
 

EUFRATE

Hardening techniques for commercial-off-the-shelf FPGA for digital telecommunication payloads

STATUS | Ongoing
STATUS DATE | 22/10/2024
ACTIVITY CODE | 5C.416
EUFRATE

Objectives

The EUFRATE project focuses on leveraging Field Programmable Gate Arrays (FPGAs) to develop adaptable, reliable, and cost-effective solutions for mission-critical applications, particularly in space missions and satellite communications. The project emphasizes several key objectives:

  • Flexibility and Reconfigurability: Utilizing reconfigurable FPGAs, the project aims to enable in-orbit updates and error correction through dynamic partial reconfiguration (DPR), essential for adapting to evolving mission needs without physical access to hardware.

  • Dependability: By employing commercial-off-the-shelf (COTS) FPGAs, the project seeks to ensure system reliability in harsh environments, using innovative error correction and fault tolerance techniques to maintain operations even in the event of hardware failures.

  • Cost-Effectiveness: The project balances custom FPGA designs with the practicality of COTS FPGAs, delivering high-performance systems that are both efficient and economical.

  • Scalability: Developing a scalable FPGA-based computing cluster, EUFRATE targets large-scale computing applications, enabling flexible communication and efficient task distribution within the cluster.

  • Satellite Telecommunications: Advancements in satellite communications are pursued through Software-Defined Radios (SDRs) on FPGAs, aiming to create adaptable and cost-effective communication systems.

Overall, EUFRATE aims to address current and future challenges in space missions and satellite communications through innovative FPGA-based solutions.

Challenges

Key challenges encompassed both technical and organizational aspects. Technically, implementing Dynamic Partial Reconfiguration, ensuring seamless communication within the four-board cluster, and achieving the required number of Programmable Functional Units to meet stringent performance criteria were significant hurdles. Organizationally, coordinating efforts across three distinct workgroups and facilitating efficient information exchange posed challenges. Despite these challenges, both technical and organizational aspects were successfully managed, contributing to the overall success of the project.

System Architecture

The system architecture developed is centred around a highly scalable and resilient FPGA-based cluster, utilizing a mixed-mesh topology to optimize communication and performance. Figure 1 show the setup used for testing the system, with one tile implemented for the tests and the Spacecraft emulator as well.

Figure 1 Testbed setup
Figure 1 Testbed setup

Within each tile, nodes are interconnected using a wormhole router with an XY-routing algorithm, facilitating efficient data transfer through packets. The Aurora protocol, chosen for its scalability and high data rate, handles communication within and between tiles, connecting a maximum of four FPGAs per node to minimize link requirements while maximizing the cluster’s scalability.

The architecture also includes a robust control system using I2C protocol, allowing nodes to operate as either Master or Slave, dynamically sending and receiving data as needed. This setup supports over 100 nodes, ensuring scalability and efficient management of the cluster.

Key components include the Blazes and BaByloN Processing System, featuring microprocessors dedicated to cluster management and application-specific computations, and the TMR Beacon Controller, which monitors the health of the nodes and triggers dynamic reconfiguration when necessary. The architecture also incorporates an array of PFU-based accelerators for handling parallel and compute-intensive tasks, and a DDR4 Memory Controller for managing external memory access. The combination of these elements ensures a robust, high-performance system capable of meeting the project’s demanding requirements.

Figure 2 reports the high-level block diagram implemented for the testbed setup.

Figure 2 Testbed block diagram
Figure 2 Testbed block diagram

Plan

The project started on May 31st, 2021; the milestones outline key phases over 24 months. After the Kick-Off (KO), the project progressed through various reviews, including the System Requirements Review (SRR), Preliminary Design Review (PDR), Critical Design Review/Test Readiness Review (CDR/TRR), and the Test Review Boards (TRB). The project concludes with a Final Review (FR) and Final Presentation (FP). 

Current Status

The project is successfully completed. The Final Review and Final Presentation have been concluded, marking the end of all planned activities. The design has been finalized and validated through comprehensive radiation tests, which yielded positive results. These tests confirmed the project’s objectives, demonstrating the effectiveness of the proposed solutions. All milestones have been achieved, and the outcomes align with the initial goals, showcasing a robust and reliable design.

DIPRET

Digital Predistortion Techniques for Beamforming and Intermodulation Improvement of Active Antennas

STATUS | Ongoing
STATUS DATE | 30/09/2024
ACTIVITY CODE | 5C.458
DIPRET

Objectives

The objective of the proposed activity is to develop and test efficient broadband digital pre-distortion algorithms and architectures for payloads utilising digital processors.

The developed concept shall be implemented in a combined RF and digital processor testbed.

Tests in a laboratory environment will be carried out to fully evaluate the performance improvements. The basic idea is to consider at least 16 independent transmitting beams generated by a multiple-beam smart antenna, each one capable of using a transmission technology of something as 12 subcarriers organised in an OFDM architecture.

The amplifiers connected with the active antenna array should be linearised to target the following improvements:

  • at least 10% improvement of payload capacity/throughput

  • 30% higher signal C/I

  • up to 5% DC-to-RF efficiency improvement

Challenges

The PA is a key element required in every communications system to strengthen the transmitted signal to compensate for the wireless radio channel losses.

The principles of predistortion linearisation are straightforward and precede the PA with a subsystem that counteracts the nonlinear characteristic of the PA.

The main challenge is to create a DPD capable of significantly reducing the output level of intermodulation.

In this case it would become possible to reduce the transmission back off (by increasing the output power level)), improving the efficiency of the transmission channel and at the same time improving the link budget.

Other important challenges are:

  • make effective the DPD inside in a large bandwidth, in fact the DPD performances are typically better in a narrow band context;

  • make effective the DPD by observing the return RF feedback by a reduced number of RF paths, so reducing the complexity of the hardware and of the digital algorithms.

Other challenges are to create a test bed capable of making the benefits of DPD fully evident.

For this reason, it is necessary to pay close attention to the performances of the RF and digital boards, in terms of:

  • digital resources of the Digital module to generate modulated tones with beamforming and multi-beam capabilities;

  • adequate spurious suppression related to the RF up-conversion process in the RF paths;

  • Phase and amplitude matching of all the RF paths, in order to make them as similar as possible in performance.

System Architecture

The developed concept will be implemented in a combined RF and digital processor test-bed.

The test-bed can simulate the behaviour of the system, it is composed of the digital and the RF parts (RF part also contains the radiating elements) and by the necessary laboratory instrumentation.

The Digital module contains the following main functions:

  • generation of multiple modulated tones;

  • beamforming along four RF paths;

  • digital pre-distortion of the conducted signal through the four RF paths.

  • AD and DA converters.

The RF part is formed by four paths, everyone contains: 

  • the Up-conversion stage for the forward signal routed to the radiating element;

  • the Down-conversion stage for the feedback signal routed to the Digital Module.

Test measurements will be made inside an automatic test procedure, involving the test-bed together the instrumentation.

The external computer will be connected to the test-bed through standard ethernet/USB interfaces and to the instrumentation through standard ethernet/IE488.

Plan

The program foresees a detailed design of a validated Digital Pre-Distortion (DPD) techniques and combined RF and processor testbed with accompanying algorithms in source code, the realization of the prototype and the verification of the characteristics.

The program duration is 24 months with the following timeline:

The following milestones are foreseen during the 24 months of activities:

  • a Specification Requirements Review (RR)

  • a Preliminary Design Review (PDR)

  • a Detailed Design Review (DDR)

  • an Implementation Review (IR)

  • a Test Readiness Review, (TRR) at the completion of prototype implementation;

  • a Final Review (FR) and a Final Presentation, at the end of the activities.

Current Status

The project is started on 01/07/2024 and a KO meeting between ESA and ITS/Consorzio ULISSE has been held.

High Temp PSU for SSPA

High Temperature, Modular and Flexible Power Supply for Ka/Q/V-Band Solid State Power Amplifier

STATUS | Ongoing
STATUS DATE | 30/08/2024
ACTIVITY CODE | 5C.409
High Temp PSU for SSPA

Objectives

The aim of the project is to develop a power supply for Ka/Q/V-Band Solid State Power Amplifiers (SSPA) and associated technologies. The power supply should be modular, flexible and capable to function at high temperature. The temperature requirement refers to an increased temperature compared to conventional baseplate regulation and in this case was set to 85°C. Modularity addresses the need to have a solution capable to supply a variable amount of SSPAs by stacking or assembling modules. Finally the flexibility refers to the possibility to have different input and output voltage, in order to bring flexibility regarding Bus Voltage as well as different SSPA technology. 

Technology demonstrator will be manufactured as well as an electrical model with relevant technologies implemented. The electrical model shall be tested under vacuum, with a regulation at 85°C.

Challenges

The challenges of the projects are related to system, technology and electrical topology. System architecture should be understood in order to propose a relevant solutions for SSPAs. Compatibility to temperature is a challenging part as it is 20°C higher than conventional baseplate regulation. Finally there is a challenge related to electrical topology and the requirement to have a flexible and modular solution.

System Architecture

At system level, integration of the power supply and the SSPAs will depend on the antenna architecture. For Ka/Q/V bands, the narrow distance between radiating elements makes it a requirement to have a remote power supply and to use harnesses to connect the SSPAs. Typically, SSPA antennas have their own cooling loop (different from the satellite baseplate) in order to manage the important dissipation of the amplifiers. A power supply compatible with higher temperature regulation makes it possible to integrate the module close to the antenna which is a benefit at system level. 

Plan

The project plan is the following : 

  • System architecture & Requirements 

  • Architecture Design 

  • Detailed Design 

  • Implementation and manufacturing 

  • Tests, compliance to specifications and roadmap

Current Status

Project has been completed successfully.

From early concept including new technologies to electrical testing under vacuum conditions at 85°C. The model is capable to supply 8 SSPAs (max 5A, 25V), for a total output power of 1kW. 93.5% Efficiency was measured under vacuum conditions with a regulation at 85°C.
 

DOMUK

Dielectric-loaded high-power Output de-MUltiplexer at Ku/ka-band

STATUS | Ongoing
STATUS DATE | 30/08/2024
ACTIVITY CODE | 5C.361
DOMUK

Objectives

This project activity aims at developing Ku-band and Ka-band compact high-power ODEMUX (Output Demultiplexer) based on ceramic-loaded resonators to be used in next generation on-board satellite systems. A review of the most suitable concepts for compact ODEMUX based on ceramic-loaded resonators will be carried out with emphasis on filter high-Q performance, thermal stability, high-power handling in space environment and compactness. The activity will trade off and select at least two baseline concepts for Ku-band and at least two concepts for Ka-band and will produce a detailed design of breadboards (BB) in phase 1 and of engineering models (EM) in phase 2. The EM will be based on the more promising baselines selected at end of phase 1. Finally, an extensive test campaign will be performed on the two EM ODEMUXs at Ku-band and Ka-band. 

Challenges

Dielectric-loaded resonators allow to significantly reduce mass and size of high-Q filters. In particular, ceramic materials allow both for significant size reduction (thanks to their high relative permittivity) and for high-Q (thanks to their high QxF factor). Compact filters, anyway, risk to be very sensitive to manufacturing tolerances of the ceramic parts. Moreover, power-handling risks to be critical mainly because ceramic materials does not allow for a good thermal flow as metal materials and because their Multipactor features need to be studied case by case. Custom designs and studies in combination between electromagnetic and thermo-mechanical domains need to be performed to carefully evaluate, trade-off and mitigate risk of thermal instability and criticality in high-power operating conditions.

System Architecture

In satellite, a single Travelling Wave Tube Amplifier (TWTA) is shared between two or more beams in current multi-beam (Ku/Ka-band) on-board systems. This is in order to reduce the number of high-power amplifiers embarked on the satellite. In this scenario an Output De-Multiplexer (ODEMUX) can be employed after the TWTA to separate the signals destined for each beam.

Plan

The entire work of the project is organized and divided into two technical and contractual phases. 

In the first parts, the most promising technology concepts are planned to be tested at BB level, leading to the final design concept selection. In the second part, EMs close to a final product have to be designed and subjected to an extensive environmental and RF test campaign.
 

Current Status

The project is finalized. 

FR meeting of the project is scheduled in May 2024.
 

TANNDEM

DEMODULATOR SUPPORTED BY ARTIFICIAL NEURAL NETWORKS

STATUS | Ongoing
STATUS DATE | 16/07/2024
ACTIVITY CODE | 7B.065
TANNDEM

Objectives

The TANNDEM project aims to design and test a demodulator supported by an artificial neural network (ANN). This demodulator will be part of current communication standards such as 5G, DVB (Digital Video Broadcasting), Consultative Committee for Space Data Systems (CCSDS), and Internet of Things (IoT) for physical layer processing tasks: demodulation, de-mapping and channel decoding in satellite communication (Satcom) applications.

Within the demodulator, the Forward Error Correction (FEC) is the block that accounts from the most part of the computational complexity. FEC is a channel decoding scheme crucial to modern digital communications systems. Low-Density Parity-Check (LDPC), Reed-Solomon or Polar codes are examples of FEC algorithms used in different communications standards such as DVB or 3GPP (4G, 5G and future 6G). FEC decoding algorithms are typically the element of the receivers that require more complex computational capacity regarding resources. This computing problem is increased and aggravated in high data rate communications. Reducing the implementation complexity in communication receivers and the power consumption of FEC algorithms has become essential to evolving future communication systems to increase throughput. In addition to channel decoding, other physical layer tasks, such as demodulation and de-mapping, demand enormous resources in current communication receiver implementations. These resources can be the number of computations or processes to perform in each task, the computation time or the number of hardware components used in the implementation as logic gates.

From the point of view of satellite communications (Satcom), reducing power consumption and processing time is vital due to its repercussion on the payload size and, consequently, on the cost. To integrate with terrestrial networks, satellites must reduce latency and delay. Reducing the processing time favours the previous reduction or compensates for the least latency and delay innate to Satcom’s nature.

Challenges

Satellite communication has been playing a significant role in wireless communications due to its ability to offer omnipresent wireless coverage. In particular, low Earth orbit (LEO) satellites are able to enhance communication performance by reducing over-the-air delay and path loss due to the shorter link distance. Most commercial LEO Satcom systems are improving thanks to the third-generation digital satellite television broadcasts (DVB-S2/S2X). As 5G networks are developed, the interest in combining LEO satellites with 5G networks is growing. Nevertheless, to provide dual-mode communications using both satellites and terrestrial networks, DVB-S2X must incur high costs. Moreover, when compared to 5G, DVB-S2X lacks features like uplink synchronization, HARQ, and a control channel. Furthermore, the orthogonal frequency division modulation (OFDM) method can offer the bandwidths required for future space communication. For instance, as reported in, the Ku-band Starlink downlink is most likely based on OFDM.  We then choose the 5G NR standard for the software demodulator’s implementation due to its higher flexibility and promising higher performance.

Figure 1 illustrates a simplified conventional communication system for satellite communications. First, the desired bit stream is augmented by adding proper redundancy via channel coding. Then, the bits are mapped to symbols using quadrature amplitude modulation (QAM). This generates the waveform for the signal. This waveform is important because it is related to features such as power. Next, to address the interference related to the multipath nature of the propagation environment, the OFDM scheme is added. The signal is converted from the frequency domain to the time domain via the inverse fast Fourier transform (IFFT, and the cyclic prefix (CP) is added. Finally, the signal is transmitted. At the receiver side, shown in Figure 1, all the processes carried out on the transmitter side must be undone until we can recover the transmitted bit stream. During the training phase, pilot signals are sent to estimate the channel and then used in equalization during the data phase.

Among the tasks mentioned above, channel estimation and equalisation, decoding and demodulation are the physical layer tasks that consume the most of the resources in a conventional receiver, such as power consumption. In addition, they require a large computation time and many operations. Accurate channel state information (CSI) is critical for the performance of wireless communication systems since this information is the basis for subsequent tasks such as adaptive modulation, beamforming, and other link adaptive technologies in the current modern systems.

System Architecture

The implementation is carried out using MATLAB and Sionna Software, while the verification is carried out in Sionna for the SW part to successfully implement and test the ML algorithm and the associated measurement methodology, and with hardware-in-the-loop in a Xilinx Versal AI for realistic power consumption and complexity assessment.

  • Detailed implementation schedule
  • The detailed implementation schedule is explained in the following points:
  • Design and Preparation: The first step, corresponding to the first month of the WP4, is dedicated to the investigation of the potential ML algorithms candidates. The design and preparation phase aims to inspect the available data that is needed to train our model and specify our ML model’s requirements. We use these requirements to design the architecture of the ML application, establish the serving strategy, and create a test suite for the future ML model. In addition, the Sionna implementation environment has to be set up. An HPC server account has to be created and the user has to increase the knowledge of the environment (e.g. Matlab scripts, parallel simulations etc).
  • ML development and performance evaluation: In this second step, a simulation framework in Matlab is implemented to characterize the relevant key performance metrics of the decoder and to create the training data for the ML algorithm. The dataset is generated offline. Here, we run iteratively different steps, such as identifying or polishing the suitable ML algorithm for our situation and the relevant performance indicators, data generation and engineering, and model engineering. In ML development, multiple experiments on model training can be executed in parallel before deciding on what model is promoted. We specify the ML parameters and scripts, and training and testing data. The primary goal in this phase is to deliver a stable quality ML model. The goal of this part is to have an accurate dataset to train the ML algorithm. If needed, a High Computational Computing server is used. The dataset is reproducible and made available online.
  • Data evaluation and analysis: The dataset obtained is used to obtain the accuracy data with ML implemented on Matlab. This phase is crucial in order to demonstrate the effectiveness of the proposed models and algorithms subject to the actual environmental variations. Extended data sets can be generated with the SIGCOM Labs facilities at these points after the exact system model has been defined in the MATLAB environment. We accurately quantize the accuracy of the model, using several key performance indicators (KPIs) to quantize the Performance, Power Consumption, and Complexity.

 

  • Calibration and Profiling: Before the hardware implementation, the code is profiled and quantized using Sionna. Quantization makes it possible to use integer computing units and to represent weights and activations by lower bits, while pruning reduces the overall required operations. Profiling is needed to identify parts of the software that need to be accelerated. Once this step is completed, the algorithm is ready for hardware implementation.
  • Proof of concept: The implemented software is implemented on the hardware using, on one hand, the Sionna implementation in GPU, and on the other hand, the AI acceleration chip from Xilinx (Versal AI) for realistic KPI evaluation on the complexity and power consumption. The obtained output is compared with the output obtained using the software only and the benefits of hardware implementation is demonstrated by comparing to known benchmarks (e.g. FPGA utilization, processing time in the GPU, etc). The exact KPIs is defined in due time during the project execution.

 

List and description of the facilities (hardware and software)

  • Software
  • Matlab (available on a local computer and centralized server at the university), Sionna implementation software,
  • Sionna | 5G & 6G Physical Layer Research Software | NVIDIA Developer
  • Vivado ML edition 2022.
  • Sionna™ is a GPU-accelerated open-source library developed by NVIDIA for link-level simulations based on TensorFlow. It enables the rapid prototyping of complex communication system architectures and provides native support for the integration of neural networks. Sionna implements a wide breadth of carefully tested state-of-the-art algorithms that can be used for benchmarking and end-to-end performance evaluation. In TANNDEM, Sionna is used to test and validate the proposed models for the demodulator supported by ANN. Sionna is a powerful tool capable of implementing wide range of tested SOTA algorithm useful for doing benchmarking and performance evaluation in end-to-end wireless communication. This makes Sionna valuable tool for extensive physical layer research on 6G wireless communication system.
  • The building blocks in Sionna are developed and extended continuously by the NVIDIA to carry-out wireless communication physical layer research. It supports a growing set of features, such as multi-user multiple-input multiple-output (MU-MIMO) link-level simulations with 5G-compliant low-density parity-check (LDPC) and Polar codes, 3GPP TR38.901 channel models, orthogonal frequency-division multiplexing (OFDM), channel estimation, and more. Every building block is an independent module that can be easily tested, understood, and modified according to your needs.
  • Sionna provides a high-level Python application programming interface (API) to easily model complex communication systems while providing full flexibility to adapt to your research. Based on TensorFlow, Sionna scales automatically across multiple GPUs. Since Sionna is Tensorflow based platform, it provides Keras layers for complex communication architectures. As the components in Sionna are implemented as Keras layers, so it lets users build sophisticated system architectures by connecting the desired layers in the same way to build a neural network.
  • The key features associated with the first release of the Sionna are:
  • 5G LDPC, 5G polar, and convolutional codes, rate-matching, CRC, interleaver, scrambler 
  • Various decoders
  • QAM and custom modulation schemes 
  • 3GPP 38.901 Channel Models (TDL, CDL), Rayleigh, AWGN 
  • OFDM 
  • MIMO channel estimation, equalization, and precoding 

 

Hardware

  • The implementation steps is organised along the 8 months planned for WP4 in the project in such a way that the hardware SIGCOM lab facilities are available. The training data generation, algorithm simulation, and results collection take most of the planned timeline. A detailed list of the implementation steps, equipment and time effort needed is prepared in due time, together with a traceable verification and test plan, including an accurate description of the measurement tests.
  • The summarized list and description of the facilities (hardware) available at SnT are as follows:
  • Centralized high-performance computers and servers at SnT (“regular” nodes: Dual CPU, no accelerators, 128 to 256 GB of RAM.
  • “GPU” nodes: Dual CPU, 4 Nvidia accelerators, 768 GB RAM, preferable- NVIDIA RTX A6000 workstation GPU:  It has specs, technology, and bundled software to ignite performance in any workstation’s inner workings. The RTX A6000 has 10,752 CUDA cores, 84 RT cores, and 336 Tensor cores to provide general graphics processing speed and increased speed and number of ray tracing and AI inference operations. It also has a massive 48GB of RAM and a 768 GB per second peak memory bandwidth. You can even link two RTX A6000s together with NVLink. The RTX A6000 supports high dynamic range (HDR), and can output to up to four monitors simultaneously.
  • “bigmem” nodes: Quad-CPU, no accelerators, 3072 GB RAM
  • Versal AI Core Series VCK190 evaluation kit: This chipset from 
  • Xilinx is a perfect blend of adaptive signal processing and ML, capable of targeting ML focussed signal processing applications.  In terms of performance, it is at the top of the food chain.
  • Versal AI Core Series VCK5000: The VCK5000 also known by DPUCVDX8H is a high throughput and high performance NN processing engine by Versal AI core. It supports Vitis-AI development environment capable of accelerating AI interface on Xilinx hardware platform. The VCK5000 enables high efficiency and it unleashes the full potential of AI acceleration on Xilinx chips. The general hardware analysing of the float-based CNN model requires highly intensive computation requiring high bandwidth of memory for the low latency and high throughput of the operation. Therefore, the quantization is employed to achieve high performance with less computation and memory. The quantization allows representation of weights and activations with lower bits integer computing units.

Plan

The work to be performed in each WP is summarized below:

 

WP 1.0: Literature Review and Application Scenario Definition

Objective: definition of the application into which the demodulator is integrated, SoTa review and establish the end-user requirements and quantify the advantages of using the new demodulator with respect to SoTA alternatives.

Output: TN 1 is composed of TN1.1 and TN 1.2.

 

WP 2.0: Technical Baseline and Design

Objective: identification of the technical baseline that offers the best potential for the development of a demodulator based on an artificial neural network (ANN). To do so, preliminary simulations based on technological options are foreseen to select the best ANN topology that it can satisfy the technical requirements.

Output: TN 2 is composed of TN2.1 and TN 2.2.

 

WP 3.0: Definition Plan of Demodulator

Objective: focused on all detailed plans necessary to successfully implement and test the deliverable items and verify their compliance with the technical specifications.  

Output: TN 3.

 

WP 4.0: Development and Testing of Demodulator

Objective: development of the SW related to the demodulator, followed by the testing campaign and the reflection and analysis of the results. It is the longest WP in this activity as it also includes a final task where compliance with requirements and potential corrective actions are considered. Therefore, we foresee this task to take a significant portion of the total project time

Output: TN 4 is composed of TN4.1 and TN 4.2.

 

WP 5.0: Outline and technology

Objective: a critical assessment of the potential of the developed items for commercial exploitation and establishes a development plan to further raise their TRL and thereby bring them to market readiness. Disseminate the findings and identify the technical, non-technical and standardization gaps that exist for implementing and commercialize the demodulator developed and tested in WP 3 and 4. Propose how these gaps should be addressed and develop a roadmap of key workstreams, activities and outputs.

Output: TN 5.

 

WP 6.0: Project Management

Objective: It is dedicated throughout the project to the management, coordination of the different tasks, dissemination, documentation, and project meetings.

Output: FP, FR.

Current Status

As of November 2023, the TANNDEM project is working on its WP1 with definition of the scenarios and requirements, definition of the ML algorithms and their framework, generation of the training data sets, and selection of the AI chipset family.

 

The team will work towards the defining of the ML algorithms in the WP2 of the project.

HVAC PCB

Acceptance criteria for defects and ageing effects in high voltage EPC and PPU printed circuit boards.

STATUS | Ongoing
STATUS DATE |
ACTIVITY CODE | 5C.460
HVAC PCB

Objectives

The objective of the activity is to design, manufacture and evaluate test samples in order to derive acceptance criteria of defects and ageing effects in high voltage printed circuit boards of EPC and PPU using voltages higher than 500V. As example (non-exhaustive cases) :

(void)
(void)
(Fiber)
(Fiber)

Challenges

The main challenges of this activity are the following :

  • to develop techniques to inject reproducible defects into PCBs for test purposes

  • to predict and verify ageing effects, life limiting-factors and the impact on screening yield. 

  • to study the effects using a theoretical approach and conduct associated verification tests, 

  • to derive rules for screening and acceptance and develop automated screening methods, 

  • to derive pass fail criteria for acceptance of defects 

  • to review design rules

System Architecture

The PCB topologies that will be assessed in this study are intended for high voltage applications; the results of this activity will therefore be usable for the design, the manufacturing and the test of the following High Voltage products/architectures :

  • Electronic Power Conditioners (EPC) up to 10kV.

  • Power Processing Units (PPU) up to 1.6kV.

Plan

Existing approaches for optimised PCB procurement and design rules for low voltage PCBs shall serve as a starting point. Considering high voltage specific requirements and problem areas, an important part of this project is to design and manufacture hardware high voltage PCB samples/breadboards to carry out verification testing. 

The study logic (including a short description of each work package and the reviews of the project) is visible here below : 
 

diagram

  • RR : “Requirements Review” with the objective to define a complete, self-standing and traceable set of technical requirements for the deliverable items. 

  • BR : “Baseline Review” with the objective to select the technical baseline that offers the best potential to achieve the activity objectives.

  • DR : “Design Review” with the objective to establish a detailed design and demonstrate, by appropriate analyses, simulations, tests or other means, that it can satisfy the technical requirements. 

  • TRR : “Test Readiness Review” with the objective to establish all detailed plans necessary to successfully implement and test the deliverable items and verify their compliance to the technical specifications. 

  • TRB/FR : “Test Review Board”/”Final Review” with the objectives to Implement the deliverable items, quantify their performances by means of a suitable test campaign and demonstrate compliance to the technical requirements and to perform a critical assessment of the potential of the developed items for commercial exploitation

Current Status

The “Acceptance criteria for defects and ageing effects in high voltage EPC and PPU printed circuit boards” has been launched ; the kick-off of the activity has been held the 18/01/2024.

The first step of the activity is now ongoing.

So, the project activity starts with :

  • A technical survey of the state-of-the-art (incl. literature, patents, commercially available products and technologies).

  • A Critical Assessment of the State-of-the-Art.

  • The finalized technical specification of the activity.

  • The definition of the outline verification plan of the activity.

OBFC

On-board feed chain for combined Q, V Band feeder and Ka-band user links

STATUS | Completed
STATUS DATE | 25/03/2024
ACTIVITY CODE | 5B.193
OBFC

Objectives

The study is relevant to the next generation broadband telecommunication service (VHTS) based on Single Feed Per Beam, developing an Engineering Model (EM) of a demanding innovative feed system operating from 17.7 GHz to 51.5 GHz providing simultaneously user and feeder link service.

The Feed system development has been addressed considering its application in operative scenarios:

  • Provision of multi-media services at high data rate.

  • Compatibility with small user terminals.

  • High/very-high throughput supported by payload on board a geostationary satellite.

  • European service area with focus on national mission needs.

  • multi beams system solution in Ka/K band for user link and Q/V band for feeder link.

  • Users coverage over Europe and Gateways concentrically aligned over the users coverage

  • Medium size satellite platform compatible with medium/large class of launchers

  • Board tracking system planned

  • Compatibility with innovative electric propulsion system platforms

  • Payload having a target mass of 400 Kg and a target power of 4 KW

The main design objectives have been:

  • To guarantee proper RF performance over an extremely wide spectrum range 

  • Tunable approach to be easily customized for a given antenna system

  • Compact envelope to be accommodated in a feed cluster

Challenges

At current state of the art a feed system involving the User and Feeder bands has not been developed.

The main design challenge is to guarantee in a compact envelope (cross-section within 45 mm) RF performances over so different bandwidths (K/Ka vs Q/V) in terms of proper radiation patterns, Ohmic losses, XPD, Isolation, tracking capability.

System Architecture

The selected modular architecture of optimized feed system is composed by 3 main subsystems:

  • Quadriband subsystem: it includes a smooth-wall quadri-band feed-horn and the coaxial OMJ which separates the K/Ka-band signals from the Q/V-band ones (user bands (K/Ka) are extracted (injected) in the external part of coaxial structure meanwhile the feeder bands (Q/V) are propagating in the inner coaxial part)

  • K/KA recombination network: it separates the K and Ka-band signals. It consists of the cascade of a recombination turnstile OMT that couples the signals entering at the four rectangular-waveguides connected to the quadri-band sub-system to a common square waveguide. The recombination turnstile OMT consists of a turnstile junction in square-waveguide loaded with four chamfered L-junctions. The K/Ka band polarization/frequency-diplexing network consists of an asymmetric OMJ with two longitudinal slots used to couple the K-band signals to two rectangular waveguide arms

  • Q/V recombination network: it separates Q and V band and polarizations. It is composed by the cascade of: an irises polarizer, a wide band OMT and a diplexer

diagram

The selected feed system baseline direct configuration has 6 active ports:

  • 2 active ports for user link (1 polarization for K band and 1 polarization for Ka band)

  • 4 active ports for feeder link (2 polarization for Q band and 2 polarizations for V band)

  • 2 loaded ports for user links and no ports for tracking.

Plan

The Study is characterised by seven major milestones marking the development of the technical tasks:
MS1: System Requirement Review (SRR)
MS2: Preliminary Design Review (PDR)
MS3: Critical Design Review (CDR)
MS4: Manufacturing Readiness Review (MRR)
MS5: Test Readiness Review (TRR)
MS6: Test Review Board (TRB) 
MS7: Final Review (FR)

The project Work Breakdown Structure (WBS) is reported in the following figure.

diagram

Current Status

The project started in October 2020; the SRR was held in February 2021, has been completed in October 2023 with the Final Review.