PAGE CONTENTS
Objectives
The project aims at building a frequency synthesizer chip that is suitable for various applications, such as on-board clock generation, RF frequency synthesis, clock cleaning and jitter filtering. To this end, the rad-hard frequency synthesizer chip can generate a wide-range of output clock frequencies (1 MHz ~ 2.5 GHz). It has extremely low jitter (0.46 ps rms), and outstanding phase noise performances (<-99 dBc/Hz at 100 kHz offset frequency). It also features a high resolution (1 ns) PWM signal generator that provides optimal control for switching power supplies. The targeted power consumption of the chip is below 100 mW.
The ASIC is hardened against both total-ionizing-dose (TID) effects and single-event effects (SEEs), such as single-event latch-up (SEL) and single-event upset (SEU). The design target for TID hardness is taken to be greater than 100 Mrad, to cover applications in space, nuclear and high-energy physics. The targeted SEL/SEU tolerance is set to be higher than 120 MeV·cm2/mg. Radiation-hardened-by-design techniques at all levels (e.g., transistor, topology, circuits, and layout) are employed to achieve these ambitious goals.
Production of a silicon prototype of the frequency synthesizer system-on-chip in the chosen CMOS process is part of the project scope, as well as testing in both lab and relevant radiation environments.
Challenges
The added value of the outcome of this project towards future customers spreads out over various aspects, in particular the technical specifications and the multi-use of the product. The low noise, high radiation tolerance and wide frequency range together with the additional high duty-cycle resolution pulse-width modulator functionality makes this whole project challenging.
System Architecture
On the reference side, a user can provide its own system or master clock via the external reference input or use the on-chip tuneable crystal oscillator that works with an external quartz crystal.
The reference clock serves as an input for the wideband frequency synthesizer. The synthesizer is fully integrated and does not require external components. The chip output can be generated as an LVCMOS signal up to 200 MHz or as an LVDS signal up to 3 GHz.
The chip also contains supporting analog circuitry, like a bias generator, LDO’s and a temperature sensor.
A serial interface allows accessing and programming of the chip. It can also be used to enable a diagnostics mode
Plan
- Architecture definition and block topologies.
- Ends by mid-April 2019.
- Chip design phase.
- Synthesizer development by KU Leuven Advise team.
- Full-chip development in parallel, performed by Magics.
- Intermediate design reviews.
- Prototyping phase.
- Starting February 2020.
- Chip fabrication and packaging.
- Test plan preparation for characterization and radiation assessment.
- Electrical characterization.
- The chip performance is tested under all operating conditions.
- Radiation assessment covering the rad-hard specifications.
- The project closure date is February 2021.
Current Status
The project is completed.
A prototype frequency synthesizer ASIC is achieved.
Prototype frequency synthesizer in a CLCC-28 pin package.
(credits go to MAGICS Instruments)
