PAGE CONTENTS
Objectives
The main objective of this activity is to optimise crucial and reusable algorithms for telecommunication payloads. The target is to achieve Technology Readiness Level (TRL) 4 and 50% reduction in power consumption.
Challenges
Specific features of state-of-the-art technology and hardware are exploited to reach the power optimisation objective.
System Architecture
Two evaluation kits of novel state of the art processors are used. On each, a different algorithm is benchmark, comparing, a programmable logic only algorithm, and feature specific optimised algorithm.
Draft use cases for the algorithms are a data transponder and intersatellite link.
Plan
The main activities proposed in the framework of this project are:
- 1. Define a mission scenario
- 2. From a state-of-the-art algorithm survey, select and tailor two algorithms to be power optimised.
- 3. From a state-of-the-art device survey, select 2 devices to use (at least one being a 7nm node).
- 4. Implement the reference (if not existent yet)
- 5. Implement the optimised algorithms
- 6. Both implementations for both algorithms are compared and benchmarked
- 7. Assess the power optimisation achieved and compare to the targeted 50%. This action also allows iterative improvement of the optimisation of the algorithm.
Current Status
The kick-off was held in Q3 2025.
