PAGE CONTENTS
Objectives
Aim of the FENICE project is to develop a Satellite AIS receiver Prototype, able to decode and detect the AIS messages transmitted by the ships covered by the Antenna FoV of a SAT-AIS LEO satellite, fully compatible with both existing and future AIS terrestrial transponders. The proposed implementation is fully flexible and covers both the case of on-ground and on-board processing, as well as the deployment of different antenna subsystems.
The design and development of the prototype allowed assessing in detail the performances and complexity of the innovative demodulation algorithms, implemented on the target device. A dedicated Testbed, able to generate the required AIS signals, was also developed.
The assessment of the performance and complexity of the processing was achieved by implementing on target FPGA the enhanced algorithms and technologies originally proposed by ESA, and further improved during the FENICE project. Thanks to these innovative demodulation algorithms and architecture, FENICE demonstrated to outperform all the known space-based AIS receivers.
The results of the project demonstrated that the FENICE receiver provides an excellent solution both in terms of signal processing and in terms of technology to cope with the extremely challenging C/I expected over the AIS channels as seen from the satellite.
In parallel, a complete SW Model of the FENICE receiver has been developed, to be used for payload characterization tests in the frame of SAT-AIS Phase B1 projects, and for subsystem performance evaluation in the frame of ESA CPA activities.
The items produced in the frame of the described project will be developed up to TRL 4 (Component and/or breadboard validation in laboratory environment).
Challenges
The novel aspect of the FENICE device lies in the combination of two technologies (digital signal processing and antenna) to optimize the performance of the probability of detection of AIS messages sent from the ships and received at a LEO satellite.
In fact, the FENICE AIS receiver for satellite AIS services aims at providing an innovative solution both in terms of signal processing and in terms of technology to cope with the extremely challenging C/I expected over the AIS channels as seen from the satellite.
Plan
The project was organized into four main work packages:
- System Consolidation, where the requirements have been defined, both for Prototype and final Payload. The algorithms and the architecture of the AIS receiver have also been specified in this phase.
- Design, where the Prototype (RF-IF section and Digital section) and the Testbed have been defined. Translation of the demodulation algorithms from fixed-point C-code to VHDL has been carried out.
- Manufacturing, where the Prototype and the Testbed have been manufactured and integrated. FPGA netlist has been delivered and tested on the target device. Functional tests on each subsystem have also been carried out at the integration level.
- Testing, where the performances of the demodulation algorithms as implemented into FPGA have been extensively characterized.
Current Status
The FENICE project is COMPLETED.
