PAGE CONTENTS
Objectives
The objectives of this project center on establishing a Field-Programmable Gate Array (FPGA) Rapid Prototyping Methodology for 5G NTN. Designed specifically for software developers, the framework utilizes a C/C++ application level within the SpaceStudio environment to provide system-level optimization and a full system compiler.
Key objectives include:
- SpaceStudio Enhancement: Integrating a comprehensive 5G NTN toolkit and an open-source 5G gNodeB stack into the existing environment.
- Functional Validation: Providing functional execution of the 5G NTN stack within a simulated environment.
- Automated Deployment: Developing a streamlined pipeline for FPGA-in-the-loop testing, specifically targeting hardware such as Xilinx Zynq, UltraScale+, and Versal boards.
The methodology aims to create a unified workflow that transitions seamlessly from initial software simulation to physical hardware validation.
Benefits
Our solution provides a unique competitive edge by leveraging well-known C/C++ open-source 5G stacks, allowing developers to start with proven, high-quality codebases. The primary value lies in our ability to bridge the gap for software developers; we empower those without deep HDL expertise to treat FPGAs as high-performance extensions of their software environment. By automating the transition from standard C/C++ to accelerated hardware IPs, we remove the traditional barriers to entry for FPGA design.
Central to this advantage is our FPGA-in-the-Loop (FiL) methodology. Unlike standard simulators that often provide “best-guess” performance metrics, FiL enables real-time monitoring of software execution directly on the target hardware.
This provides software developers with exact timing and throughput data, ensuring that the accelerated 5G components meet the rigorous latency requirements of real-world networks. By combining open-source flexibility with hardware-accurate verification, we offer a high-fidelity development path that significantly outpaces the slower, fragmented workflows of traditional competitor systems.
Features
SpaceStudio serves as the foundational component of the product, specifically designed to bridge the gap between software development and FPGA hardware.
Core Components and Capabilities
- SpaceStudio: The primary capability of SpaceStudio is its integrated FPGA-in-the-Loop (FiL) infrastructure. This allows software developers to execute their code on physical targets (e.g, Zynq or Versal) while maintaining a transparent link to the design environment. Unlike traditional software-only simulations, this provides cycle-accurate, real-time performance monitoring, allowing for the immediate validation of throughput and latency under actual hardware conditions.
- Open-Source 5G Stack: The product leverages well-known C/C++ open-source 5G stacks (such as srsRAN). It provides a pre-configured environment to initialize and synchronize the User Equipment (UE), gNodeB (gNB), and 5G Core, allowing developers to focus on acceleration rather than protocol implementation from scratch.
- Automated HLS Acceleration: SpaceStudio identifies computational bottlenecks in the C/C++ code and facilitates their transformation into Accelerated IPs via HLS. This capability ensures that the high-speed data processing required for 5G is handled by dedicated hardware logic while remaining accessible to software-focused teams.
SpaceStudio handles the “heavy lifting” of hardware integration, the product enables a small team to achieve the performance density of custom silicon with the agility of a software start-up.
Challenges
The primary project challenge involves orchestrating a cohesive environment to initialize the 5G Core, gNodeB, and User Equipment components simultaneously. This integration requires precise synchronisation across the entire network stack to ensure functional stability.
Furthermore, optimizing standard C/C++ functions into high-performance accelerated IPs via HLS presents a significant hurdle. Meeting the rigorous timing and throughput demands of 5G signal processing on FPGA targets necessitates advanced hardware-level refactoring and architectural tuning to achieve the efficiency required for real-time deployment in a resource-constrained development setting.
System Architecture
The architecture leverages SpaceStudio to enable software developers to work at a C/C++ application level while benefiting from hardware acceleration. The system utilizes a Full System Compiler to perform system-level optimization, identifying CPU-intense tasks within the 5G NTN stack and offloading them to the FPGA logic. This partition allows the high-performance components of the 5G gNodeB toolkit to run as hardware-accelerated IPs on targets like Xilinx Zynq, Zynq UltraScale+, and Versal boards.
For validation, the architecture incorporates an FPGA-in-the-loop setup. The FPGA hardware connects to a UE emulator via FMC Ethernet, providing a real-world data path for testing the offloaded 5G stack components. This configuration creates a streamlined pipeline where developers can transition from software simulation to hardware-accelerated execution while maintaining visibility into performance insights directly within the IDE.
Plan
The project plan features three major milestones. First, the integration of an open-source 5G gNodeB toolkit within SpaceStudio. Second, functional validation provides execution of the stack in a simulated environment. Both milestones are targeted for the Mid-Term Review. Finally, the project culminates in FPGA execution, where an automated deployment pipeline enables FPGA-in-the-loop testing on Versal boards, reaching completion by the Final Review.
Current Status
The project leverages the SpaceStudio environment as heritage. Early achievements include defining requirements for the 5G gNodeB toolkit integration. Work in progress centres on functional validation and building the simulation environment for the 5G stack. Activities about to start include developing the automated FPGA-in-the-loop deployment pipeline for Versal boards to enable hardware-accelerated execution.
