PAGE CONTENTS
Objectives
The main aim of the MARLIN project is to develop a VDE-SAT baseband receiver which integrates proposed digital signal processing (DSP) solutions to mitigate Radio Frequency Interference (RFI), in order to increase the demodulation performance of the Uplink (UL) Link IDs in presence of interference signals.
In particular, the proposed on-board VDE-SAT architecture (aka Interference-Resilient VDE-SAT Demodulator) includes signal reception techniques that enable uncoordinated satellite access schemes in the maritime bands assigned to VHF Data Exchange Systems (VDES) in presence of in-band RFI from maritime and external sources such as in-land terrestrial services.
The project objectives are achieved by means of an initial survey and analysis of state-of-the-art interference mitigation techniques, simulation of the techniques (pulse blanking, frequency blanking, notch filtering, interference cancellation and self-interference cancellation), C++/HDL implementation, testing and validation.
Challenges
The optimal solutions combine time/frequency domain techniques (such as Pulse or Frequency blanking), Interference Cancellation (IC), and Self-Interference Cancellation (SIC) in a structured, efficient manner. Given the limitations of onboard processing capacity, this may not be possible because on-board computers for small satellite platforms generally have low computational capabilities, compared to a ground-solution where it is possible to operate with high-performance hardware, such as CPU-GPU based server, especially on this scenario which involves a real-time application of mitigation techniques on baseband digital samples. Therefore, on an on-board computer (aka processing platform) it will be possible to apply a subset (not all) of the mitigation techniques in real time.
System Architecture
A high-level on-board architecture of a VDE-SAT Payload which integrates the IR VDE-SAT Demodulator on a Processing Platform includes the following features:
• The integrated antenna could be a directive antenna such Yagi or more complex VHF array antenna to apply boresight/null digital techniques;
• The VHF Signal is captured by the reception stages, i.e. the VDE-SAT Front-end, RF Transceiver and ADC stages;
• To prevent issues of compression or saturation in the RF front-end, an Automatic Gain Control (AGC) solution could be implemented. The “Gain Control” software module would adjust the gain dynamically, pre-compensating for variations to ensure that the acquired samples maintain consistent levels and avoid distortion or other unwanted effects the overall baseband raw IQ samples related to a bandwidth of 150 kHz (referred to the Upper Leg or Lower Leg, each composed by N.3 channels, 50 kHz each), are processed by the eRFI Detection & Mitigation module, in order to mitigate in-band RFI signals digitally;
• In order to manage up to N.3 UL channels, it is expected to run in parallel N.3 instance of VDE-SAT Baseband demodulators, each of one integrates the MAI SIC module;
• MAI module is separated from the eRFI detection and mitigation module because it is activated after a first round of demodulation, i.e. it is strictly related to the demodulation processes (only for Link ID20).
Plan
The main phases of the project are:
• Phase#1: Initial trade-off analysis and survey of techniques
• Phase#2: Simulation using MATLAB Models
• Phase#3: Implementation
• Phase#4: Lab and Live testing
This phased approach ensures that the RFI mitigation techniques developed for VDE-SAT systems are rigorously tested and validated through detailed analysis, simulation, implementation, and real-world testing. By structuring the development into implementation (Phase#3) and testing (Phase#4), we can ensure that the solutions are both feasible and effective in operational environments. The approach reflects on the milestone plan:
• Kick Off (T0)
• Preliminary Design Review (T0+3M)
• Critical Design Review (T0+7M)
• Test Readiness Review (T0+15M)
• Final Review (T0+18M)
Current Status
The Preliminary Design Review milestone of the project has been successfully achieved. The current status of the project is then heading to the finalisation of the design towards the Critical Design Review milestone.
