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Objectives
The project target is the development of a DVB-SH demodulator compliant with DVB-SH standard.
The s-band receiver chipset project objective is the development of a DVB-SH demodulator fully compliant with the DVB-SH standard. Moreover the demodulator is a multi-standard receiver capable of receiving DVB-SH, DVB-H and DVB-T signal.
The receiver development is targeted towards mobile reception, with integral support of code combining, antenna diversity and high Doppler resilience to enhance quality of reception in all conditions.
The receiver also supports the features newly added to the DVB-SH standard:
- 2.5 MHz bandwidth.
- Low-latency services.
A prototype of the demodulator has been built based on FPGA architecture having the complete features of the demodulator available for field-testing as well as for laboratory performance tests.
Challenges
The key issues addressed in the project are:
- Design of a multi-standard demodulator being able to support the full specification of the DVB-SH/DVB-T and DVB-H standards.
- Development of a demodulator FPGA-based prototype being able to fully implement all the demodulator requirements.
- Testing all the demodulator features (which implies thousands of different configurations), which implied the development of an automatic test bench for allowing running tests in batch-mode.
- Full characterization of demodulator performance in a wide range of mobile and fixed reception scenarios and in different configurations (TDM-only reception, OFDM-only reception, Code-Combining, diversity reception, etc).
Plan
The project is divided in three phases:
- Phase 1: System Requirements review and IP/Chipset definition. During this phase the analysis of the requirements is performed and the requirements of the demodulator are delineated.
- Phase 2: This task deals with the design of the demodulator and the implementation of the FPGA prototype, together with the testing of the prototype in the laboratory.
- Phase 3: During this task the demodulator is prepared for mass-market manufacturing in an ASIC technology.
Current Status
The project is completed.