Avionics building blocks

Space Segment - Platform

Status

Completed
Status date

2022-12-15
Activity Code

4G.025

Objectives

Architecture of Thales Alenia Space future avionics as well as methods and tools for its development, integration and verification are specified in this project. This includes:

OBC-core specification with its variability to cope with various missions needs including LEO, MEO, GEO and interplanetary exploration missions.

For Hardware:

OBC-D modules specification.
OBC-D Design Description and Design Report.
OBC-D test and validation plan.
OBC-D tests and test bench specification.
OBC-D Elegant Bread-Board specification.

For FPGA fabric:

Market and heritage survey.
IPs functions and interfaces specification.
FPGA bit-stream development.

For Boot and Hardware Dependent Software:

Boot Software specification.
Software drivers for FPGA functions interfacing specification.
Development of test equipment for IPs and IP-drivers integration and test.

For Application Software:

Selection of ARM multi-core RTOS (Real Time Operating System).
Overall software architecture definition.
RTOS and software prototype integration and test.

Challenges

One challenge of this study consists in defining the development logic for this new generation computer while following the NG-ULTRA SoC development in parallel to activities for definition and validation of Avionics, Hardware, IPs, Software and ACE. In addition, function allocation among Hardware, FPGA and Software while keeping good dependability level represents one the main challenge of the study.

Benefits

The main benefits brought by the product are, from a commercial point of view, the increased competitiveness, through reduced recurrent cost, mass and consumption.

On top of that, the product offers a high flexibility thanks to the reprogrammable FPGA and to the high computing power and partitioned software capability, allowing integration in the On-Board Software of additional application software functions for future needs.

Features

The NG-ULTRA/DAHLIA System-on-Chip is a very high-performance microprocessor based on European 28nm FDSOI, embedding a multicore ARM processor and very large FPGA. Such technology has allowed to design a new generation OBC offering very compact and flexible solution for multi-mission application.

The OBC integrates hardware and software for handling of RF signals directly from GNSS antennas. Furthermore, an OBC extension module may be added for specific mission needs.

System Architecture

Plan

Main project milestones are:

Milestone 1 on 2020 March 19th for preliminary specification review.
Milestone 2 to reach PDR level for OBC-D equipment is split in 3 parts.
- Part1 held on 2020 May 28th for review of updated specification, reliability assessment and FMEA, test plan and test equipment specification.
- Part2 held on 2020 July 23rd, for review of updated documentation and detailed specification.
- Completion held in 2020 September.
Milestone 3 is the Test Readiness Review of the hardware/software integration testing on OBC-D CORE functional model
Milestone 4 concludes the contract with the Test Review board sharing the results of the HDSW integration and test on OBC-D FUMO.