PAGE CONTENTS
Objectives
The objective of this activity is to design, simulate and test a high data rate Forward Error Correction on-board decoder and demonstrate this via a breadboard running at a data rate of at least 10 Gigabits per second (Gbps) with soft decision decoding. The decoder shall target next generation optical inter-satellite links and shall be made lightweight in terms of onboard resources usage.
Besides the breadboard-level hardware demonstration, target FEC performances at higher rates (up to 100Gbps) will be investigated and assessed.
The target TRL for this activity is 4.
Challenges
The challenges to be overcome during the activity will mostly involve the design of a lightweight FEC code to work at very high datarates. Another challenge will be the implementation of the decoder on hardware platforms with comparable capabilities of the ones currently available and/or planned for satellite communication payloads, posing a limitation on the processing performances.
System Architecture
The expected system shall consist of a hardware-based encoder, an OISL channel model, and the breadboard decoder. Of course, the encoder and decoder implementation will depend on the FEC selection and ad-hoc design.
During design and development phase, the support of software models for the communication channel and the FEC code will also allow the consortium to assess theoretical performances and limitations of the selected solution for very high data rate applications.
Plan
The project will start with a State-of-Art assessment for potential FEC candidates and available payload processing units for communication payloads. After this phase, the design of the FEC code, and the related design of the decoder breadboard and encoder hardware will follow. In the implementation phase, the breadboard will be developed and the support hardware will be setup. The test and verification phase will assess whether the expected performance of the system have been achieved, and possible deviations will be identified and investigated. The final phase will consist of a technology evaluation and of a suggestion for development roadmap to bring the concept to higher TRLs.
Current Status
The project has kicked off in September 2024.At the time of writing, the Consortium is looking into the state of the art and exploring possible solutions for FEC design and its implementations in platforms whose resources are compatible with the satellite-based payloads.





