Description

Objective: The objective of this activity is to design, simulate and test a high data rate Forward Error Correction decoder and demonstrate this via a breadboard running at a data rate of at least 100 Gigabits per second (Gbps) with soft decision decoding. The decoder shall target next generation optical inter-satellite links and shall be made lightweight in terms of onboard resources usage. Targeted Improvements:- 10 times improvement of the decoder's data rate compared to state of the art optical inter satellite terminals. - Introduce novel capability of soft decision decoders for high bandwidth satellite optical communication terminals.Description: Optical inter-satellite links (OISLs) are a key enabler for a range of LEO and GEO based missions such as EDRS, mega-constellations and HydRON. Current Laser Communication Terminals for OISLs apply low complexity block Forward Error Correction (FEC) codes(such as Reed Solomon or Bose Chaudhuri Hocquenghem (BHC) at rates of few Gbps in order to keep the decoding resources of onboard terminals reasonable. The next generation of OISLs will reach or exceed the 100 Gbps mark and are expected to require much higher coding gains that can only be attained by advanced (soft decision) decoding schemes, such as Low-Density Parity Check (LDPC), Turbo or Polarcodes. The current activity shall look at code designs that allow for practical onboard decoding of advanced FEC codes at very highspeeds, (i.e., hundreds of Gbps). After reviewing high data rate codes in existing standards (e.g. 10GBASE-T, ITU-T RecommendationsG.975 and G.975.1), the activity shall focus on the design and simulation of the selected advanced code families considering means of reducing the onboard burden of the decoding process. Such approaches could involve a combination of parallelisation in the decoding process, fast decoding convergence and hybrid soft/hard decision decoding of the advanced codes. The code design shall be tailored to the particularities of the OISL which involves very high data rates realised via low cardinality modulations (such as BPSK, QPSK, OOK). After FEC code design and simulation, prototype hardware, software and firmware shall be developed and testing of the baseline solution 100 Gbps decoder shall take place. The solution should be possibly differentiated between LEO and GEO applications, as the latter allows for higher complexity and power consumption. For testing the decoder, a high data rate DSP module generating test vectors shall be connected to the developed decoder.