13GHz Transceiver

10MHZ PLL

In the TUL204, the main 13.05GHz VCO is phase locked directly to this external 10MHz frequency reference supplied by the terminal IDU. As a consequence of this the transmitter LO phase noise is determined by the reference phase noise within the PLL bandwidth. In the TUL204E, an internal crystal oscillator is phase locked to the incoming reference using a loop with a relatively low bandwidth (40Hz compared with 30kHz for the main loop). The overall transmitter phase noise therefore becomes dependent on the characteristics of the internal crystal oscillator at frequency offsets greater than 100Hz or so and allows the new design to be operated with IDUs which do not provide a costly very low phase noise reference.

13.05GHz PLL

The existing 13.05GHz PLL has been re-developed for a considerable improvement in phase noise without major changes to the function of the circuits. Analysis of the main phase noise limitations in the loop showed that it would be possible to retain the existing L-band oscillator/5 x frequency multiplier scheme with modifications to the oscillator loading. This has meant no new methods for oscillator alignment have been required.

The PLL has however been completely re-designed. The current PLL IC has been replaced with a similar part from the same family which offers a lower phase detector noise floor but is otherwise functionally compatible with the original part. Circuit changes have arisen from the part's lower operating supply voltage range.

The loop parameters have also been optimised for minimum phase noise rather than transient response by increasing the phase margin.

The changes result in a typical phase noise improvement by >10dB over much of the spectrum - particularly the key 1kHz-100kHz region.

On Line Tuning

Achievement of the design goals of flatter gain against frequency response was made possi