Advanced Decoding Algorithms for Satellite Broadcasting

Status

Completed
Status date

2008-02-07
Activity Code

B 2.1

Objectives

The increasing demand for general broadband Digital Broadcasting Services brings the need for more efficient transmission techniques, both in power and spectrum. Advanced decoding techniques allow more efficient resources utilisation without the need to modify the existing systems.

The main objective of the Advanced Decoding Algorithms for Satellite Broadcasting project was to validate a new decoding algorithm for the DVB-S standard and to check its practical feasibility and possible implementation alternatives.

Challenges

Soft decision decoding.
Iterative decoding.
Practical feasibility of advanced decoding algorithms.

Benefits

Improvement of link budgets without modifying DVB-S standard by means of advanced decoding techniques based on soft decision information handling and iterativeness. More efficient resource utilisation.

Features

The test modules and the decoder implemented consist of the following elements:

A data generator including a binary pseudo-random generator,
A concatenated Reed-Solomon + Interleaver + Convolutional encoder,
A noise generator outputting soft-decision symbols coded on 6 bits,
An iterative Convolutional + Reed-Solomon decoder,
A control interface,
A counter device in order to evaluate the Word Error Rate and the Bit Error Rate,
A soft input soft output Reed-Solomon decoder.

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Plan

The project is split into:

Critical Review and Specifications Consolidation System specifications establishment and constraints and degradations analysis.

Channel coding stage performances analysis to assess theoretical upper bounds (BER and WER) of the concatenated code and improvement margin estimation.
Review of Existing Literature and Work and Selection of a Preferred Solution Possible soft-processing algorithms and interfaces for iterative decoding analysis (performance and complexity).

Trade-offs about performance versus implementation complexity. Selection of architecture and components for the iterative decoder.
Simulation of Selected Algorithms Architecture of the iterative decoder definition and high-level software models of the decoder generation and simulation.

VHDL models generation, simulation and implementation in FPGA test boards.

Current status

Closed.