Advanced Modem Prototype for Interactive Satellite Terminals

  • Status
    Ongoing
  • Status date
    2014-03-25
Objectives

The activity consists of developing a laboratory test-bed including a modem prototype (terminal and hub sides) implementing some innovative physical and MAC layer algorithms/techniques suitable to enhance the performance of broadband interactive satellite terminals implementing the DVB-RCS standard. The objective of these techniques is to improve performance and reduce the overall terminal-plus-service cost.

Objectives of the AMPIST Project are the design, the development and the implementation of a Return Link based on an advanced DVB-RCS to be used in a complete Test-Bed which also includes the DVB-S2 Forward Link available as results of the DEDICATION Project.
The improvements of the enhanced DVB-RCS compared with the standard are mainly:
  • Physical Layer: (i) enhanced FEC schema based on Turbo-Phi Co-decoder, (ii) high order modulation schemas and (iii) interference cancellation capabilities against ACI/COI disturbs;
  • Data Link Layer: GSE protocol;
  • Access Schema: CRDSA technique (also in Symbol- Synchronous mode);
The Test-Bed includes the interference generator and a channel emulator to allow testing the system under several conditions. In particular the Test-Bed is able to create Co-Channel and Adjacent Channel interferences beyond modelling Gaussian Channel and Oscillators Phase Noise.

Relevant system performances and design aspects, outcome of this project, will be used as input within the NG DVB-RCS standardization activity.

Challenges

This project is intended to perform:

  • Assessment of a DVB-RCS enhanced system architecture and layers;
  • Development of critical items with a clear commercial finalization;
  • Development of a Test Bed to have a realistic test environment;
  • Laboratory campaign of system-level validation tests.
Benefits

Space Engineering (SE) looks with great interest to DVB-S2/RCS evolution, which represents a very important occasion for the development of commercial products.

There are two distinct DVB-S2/RCS markets SE plans to tackle and to pursue: User Terminal (UT) and Hub.

This project gives to SE the opportunity of testing some important innovations (e.g. CRDSA and Interference Mitigation) which can improve the performances of both the UT and HUB for the next generation of these equipments.

Features
The Test-Bed basically includes:
  • DVB-S2 based Forward-Link;
  • DVB-RCS Return-Link;
  • Satellite channel emulator;
  • NCC emulator;
  • Auxiliary equipments for Test Bed control and monitoring.
The DVB-S2 based Forward-Link includes the following functions:
  • Programmable Baud Rate in the range [10,45] Mcps with 0.5 Mcps steps;
  • Programmable Roll-Off (0.2, 0.25, 0.35);
  • Modulation and coding rates: 
    QPSK 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 
    8PSK 3/5, 2/3, 3/4, 5/6, 8/9, 9/10 
    16APSK 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 
    32APSK 3/4, 4/5, 5/6, 8/9, 9/10
  • Normal and Short FECFRAME with support of pilots;
  • Support to NCR master clock distribution;
  • Static Pre-Distorsion on GW Modulator;
  • Support to ACM;
  • Encapsulation / de-capsulation of IP packets over MPE/MPEG and GSE (Generic Stream Encapsulation);
  • Buffer priority management for supporting IP DiffServ Quality of Service (QoS).
The DVB-RCS Return-Link includes the following functions:
  • MF-TDMA with a single carrier;
  • Encapsulation / de-capsulation of IP packets over GSE;
  • Symbol Rate: 128k, 512k & 2MBaud;
  • Turbo-Phi coding;
  • Modulation: 
    QPSK: rates 1/2, 2/3, 3/4, 6/7 
    8PSK: rates 2/3
  • Buffer priority management for supporting different Quality of Service (QoS).
The Return Link Channel Emulator realistically emulates:
  • HPA non-linearity;
  • Co-Channel and Adjacent-Channel Interferences;
  • Time-variant Fading;
  • Thermal Noise.
Plan

The project is divided into two phases.

  • The first phase is aimed at reassessing the requirements and at consolidating the system specifications, with the support of analyses and simulations. During this phase also the selection of the most appropriate algorithms will be carried out and documented.
  • The second phase includes three different periods:
    • Development:
      • Architectural Design;
      • Detailed Design;
      • Definition of the Test and Validation Plan
    • RL Integration and Testing.
Current status

The project is completed.

Documentation

Documentation may be requested

Last update
2025-02-05 12:53