AmpliKa

Status

Ongoing
Status date

2025-02-10

Objectives

The AmpliKa project aims to develop a high-efficiency Ka-band MMIC chipset in a Wafer Level Chip Scale Package (WLCSP) format, featuring a Variable Gain Amplifier (VGA), Power Amplifier (PA), and Low Noise Amplifier (LNA). This format offers advantages in cost, size, weight, and power over traditional packages, targeting high-frequency beamforming antenna systems for satellite and terrestrial communications. Applications include satellite and ground communications, as well as beamforming antenna arrays that may require hundreds to thousands of chipsets. Suitable WLCSP packaging will be evaluated, assessing flip-chip and Land Grid Array (LGA) options. A primary objective is to qualify the reliability of this packaging format for space use, advancing its technology readiness level (TRL) from TRL3 to TRL5.

Challenges

Thermal management: High power output amplifiers generate significant heat, requiring advanced cooling techniques to prevent degradation.
Efficiency optimisation: Balancing high efficiency and linearity, especially for Power Amplifiers, to avoid excessive power consumption.
Frequency precision: Ensuring consistent performance across specified frequencies (17.7-30 GHz) requires tight control over design parameters.
Noise minimisation: Achieving <2.2dB noise in the LNA while maintaining gain is challenging, demanding careful material and architecture choices.
VGA linearity: Ensuring efficient linear performance across the VGA’s gain range (5-20dB) without signal distortion.
Integration: Compactly integrating multiple functionalities on a single chip for space-limited designs.

Benefits

Size and weight reduction: WLCSP enables direct mounting on antenna substrates, reducing footprint and weight, ideal for compact flat panel antennas.
High-frequency performance: Minimises parasitics, enhancing signal transmission for Ka-band with improved power efficiency and lower losses.
Thermal management: Efficient heat dissipation via direct substrate integration, critical for high-frequency Ka-band MMICs.
Integration with antenna arrays: Allows seamless, high-density integration into phased-array systems for enhanced beamforming and low-profile designs.
Cost and manufacturing efficiency: Wafer-level processing and simplified assembly cut costs and manufacturing complexity.
Environmental suitability: Robust against space and terrestrial conditions; can resist moisture for reliability.

Features

This chip set includes a Power Amplifier, Low Noise Amplifier, and Variable Gain Amplifier in gallium arsenide MMIC technology. The proposed Power Amplifier (17.7-20.2GHz) delivers 29dBm peak power with high efficiency; the Low Noise Amplifier (27-30GHz) provides <2.2dB noise figure and 20dB gain; and the Variable Gain Amplifier (17.7-20.2GHz) offers 5-20dB gain with efficient linear performance. By encapsulating these components in a WLCSP package, the product offers a streamlined, robust design ideal for high-performance RF applications in space-constrained environments.

System Architecture

Power Amplifier architecture. Image credit: MMIC LAB/ESA

Variable Gain Amplifier architecture. Image credit: MMIC LAB/ESA

Low Noise Amplifier architecture. Image credit: MMIC LAB/ESA

Plan

Definition stage

Define complete product requirements and initial design for feasibility and risk mitigation.
Mid-Term Review milestone.
Establish baseline design for the technology phase.
Preliminary Design Review milestone.

Technology stage

Develop an initial breadboard chipset for component/process qualification; conduct thermal, RF, and mechanical testing.
Assess breadboard and qualify improvements.
Critical Design Review milestone.
Create Engineering version of chipset (Dev 2) for further qualification.
Qualification Test Review milestone.
Test engineering version with industry partners for verification at MMIC LAB.

Current status

The project kick-off meeting was held on 7 November 2024. The Mid-Term-Review will occur on 3 March 2025.