Artes 5.1 C-Band Doherty

Status

Completed
Status date

2019-09-05
Activity Code

5C.170

Objectives

The objective of this activity is to design, manufacture and test an EM of a space-borne high efficiency power flexible (both dynamic and static) HPA stage in C-band.

The scope of the hardware development in this activity is limited to the HPA (final) stage only of an SSPA.

Challenges

At the beginning of the project a review was undertaken to determine the most appropriate architecture in order to realise the high efficiency, it was determined that the use of a Doherty arrangement would be the most suitable. The main lesson to come out of this project was the bandwidth limitations of the Doherty amplifier. To achieve broader bandwidths it may be worth investigating moving the Doherty combining circuitry to the Die reference rather than after the matching circuitry as highlighted in the literature survey. This is however very difficult to implement with chip and wire techniques at high power due to the low impedances required of the Doherty transformers. Another approach could be to implement this in MMIC at lower power and then combine several stages to achieve the power requirements.

Benefits

With the introduction of GaN FETs the efficiency of SSPAs is steadily increasing, and is approaching the efficiency seen on Travelling Wave Tubes.

A trend seen in telecoms payloads is the migration of the service providers to digital modulation to ETSI DVB-S and S2 standards. This describes modulation methods with significant peak to average power ratios such as 16 QAM and 32 APSK. This modulation scheme requires a linear amplifier to avoid introducing errors due to amplitude and phase distortion.

A clear solution already in use in terrestrial mobile communications is to adopt a Doherty architecture, which increases the SSPA efficiency in back off while maintaining linearity.

Features

The EM is shown in Figure 1‑1, and is made up of an input splitting network driving the Main and Auxiliary hybrid amplifiers. The hybrid amplifiers themselves are identical chip and wire designs utilising a Wolfspeed GaN die in a hermetically sealable package with a mixture of high dielectric ceramics for matching purposes. Although identical in design the Auxiliary amplifier is biased in deep Class C while the Main amplifier is biased Class AB. These stages are combined with a Doherty combining circuit fabricated on Duroid 6035HT, the same as used for the input splitting circuit.

Figure 1‑1 C Band Doherty Final Stage Amplifier

Test results for the Doherty SSPA compared to an equivalent Class AB SSPA are shown in Figure 1‑2. Under CW operation a PAE improvement of 15% was achieved at 6dB OBO over a Class AB amplifier. Under multicarrier conditions a PAE advantage is shown from 16dBc NPR increasing to >10% at a further 3.5dB OBO. These results clearly demonstrate the advantages of a Doherty amplifier over a Class AB amplifier. An improvement PAE over bandwidth over a Class AB amplifier was achieved for ~7.5% bandwidth.

Figure 1‑2 Doherty vs Class AB: CW & NPR Performance

A further 5% points in PAE were achieved for both CW and multicarrier conditions by adaptively adjusting the Auxiliary gate bias as a function of RF drive level. These results are shown in Figure 2‑3.

Plan

The project split into five main tasks over a period of 17 months.