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StatusOngoing
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Status date2023-06-28
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Activity Code6A.087
The main aim of the project is to construct an economical channel emulator that specifically caters to multi-orbit constellations, by integrating readily available SRD technology with GPU technology for parallel processing. The channel emulator is optimized to support 5G, NB-IoT, and native satellite waveforms. Our primary objective is to ensure that the emulator's performance is equivalent to that of its competitors, without compromising its portability and compactness.
Achieving optimal balance among portability, performance and cost, while still covering most of relevant use cases.
Compared to its heavier and more expensive competitors, the CELEOS channel emulator is a low-cost, lightweight, and portable solution that utilizes readily available off-the-shelf hardware. CELEOS is capable of emulating all relevant satellite channel impairments, including native satellite and 5G use cases.
The following features are covered by CELEOS:
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Support for multi-orbit constellations
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Relevant satellite channel impairments, including delay, attenuation, Doppler shift, and Doppler spread, can be simulated
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Support for TLE synchronisation
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Capability to configure various emulation profiles (interference, noise, weather conditions, etc.)
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Facilitation of various input waveforms such as: satellite native, 5G-NR-NTN, NB-IoT, and eMTC
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Mobility scenarios such as 5G conditional handover and inter-satellite LEO to LEO handover can be emulated.
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The Vita49 standard (DiFi) and SigMF signal recording and importing are both supported.
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This system enables the emulation of "in-box" movement for GEO satellites
The general idea behind the architecture of the CE is to use an SDR (Software Defined Radio) to perform analog-to-digital and digital-to-analog conversion of RF signals and off-the-shelf GPUs (Graphics Processing Unit) for signal processing. The software is designed to be hardware-agnostic, being able to function with a range of both SDRs and GPUs.
Two configurations are implemented, varying in terms of hardware (SDR and GPU models), and thus in the number of supported channels and their bandwidth, but both using the same software.
Below is a high-level overview of the CE architecture:
In terms of hardware, the CE has 2 main components:
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SDR module, responsible for receiving and transmitting RF signals
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SPS (Signal Processing System) built around a GPU (also containing a CPU, RAM, SSD etc.), performing the necessary computations on the digital signal to emulate the desired channel
The 2 components described above are connected via fiber-optic cables/ USB, for the high-end/low-end versions respectively. The CE exposes physical RF RX and TX ports for the user to connect equipment. User connectivity to the SPS for control is provided by Ethernet ports and Wi-Fi.
The software components are:
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The real-time emulation program, which streams data to and from the SDR, and performs the signal processing on the GPU
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A multi-platform GUI application allowing users to connect to and manage the CE
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A program which translates the user-defined channel configuration into mathematical parameters used in the channel emulation
The project is structured into two phases: the Definition phase and the Technology phase. The Definition phase has a single milestone, which is the PCR at T0+3M. This milestone represents a critical point in the project, as it marks the successful delivery of the Performance requirements, SDR technology study, and satellite channel characteristics study. As such, it is a key indicator of progress and a critical point for decision-making.
The Technology phase has associated the following milestones: PDR, IR1, and FR, with a three-month gap between each phase. Each milestone has specific objectives and deliverables that must be completed before moving to the next milestone. At PDR, which is at T0+6, some of the channel impairments are implemented and a first demo is conducted. This demo is used to validate the initial performance of the technology and identify any issues that need to be addressed.
Before the IR1 phase, at T0+9, the remaining channel impairments are implemented and basic functionalities are validated. Additionally, the GUI is completed and available for use. This phase marks a significant milestone in the project, as it represents the completion of the initial development phase and the transition to the testing and optimization phase.
Between the IR1 and FR phases, the focus is on optimizing and fine-tuning the performance. This phase is critical for identifying and addressing any remaining issues with the technology and ensuring that it meets the performance requirements established in the Definition phase. Throughout this phase, an extensive testing and optimization campaign is conducted, in order to ensure that the technology is ready for deployment.
The Definition phase is successfully completed and Technology phase afferent work is underway on additional impairments, as well as on the web API that shall serve the GUI application.
The development efforts so far have been centred on the emulation program, which has been coded in C++ and CUDA. Furthermore, there has been a focus on identifying appropriate mathematical models to accurately describe the channel that is being emulated.
The Channel Emulator (CE) is capable of introducing four impairments concurrently, while conforming to specified bandwidth and latency parameters. These impairments include delay, distance attenuation, Doppler shift, and Doppler spread, which can be independently configured across four channels.
A preliminary trial of the CE was conducted at the Fraunhofer Institute for Integrated Circuits, utilizing a 5G OAI GEO satellite arrangement, which involved substituting the original Keysight emulator with CELEOS. The observed channel characteristics were comparable to those of the original emulator.
Additional work is ongoing, to incorporate more impairments into CE and to establish a web API that forms the foundation of the GUI application.
