PAGE CONTENTS
Objectives
DTP NG project deals with the development and qualification of the next generation of Digital Transparent Processor (DTP) based on 28nm ASIC and optical high speed serial links technologies. Such DTPs will be able to process up to 2500 MHz useful band per access and to present high modularity for offering more than 360 GHz routing capacity compatible with applications ranging from FSS/BSS, HTS & V-HTS needs.
Challenges
The main function of the DTP is to perform transparent and flexible routing between input and output RF ports in C band with a complete flexibility in frequency plan.
The keys drivers of DTP development are linked to the introduction of new technologies needed to reach the overall performances, mainly :
- 28 nm FDSOI ASIC technology allowing to implement both ADC and DAC functions within the ASIC.
- Optical links allowing to speed up communication between DTP modules and to drastically reduce the harness complexity.
System Architecture
DTP architecture is based of 5 functional blocks :
- Reception function in charge of input signal analog to digital conversion. It includes RF input interfaces, Analog to Digital Conversion stage, digital processing, a reference clock interface, TMTC interface and power supplies.
- Routing function in charge of routing data between Reception and Transmissions functions. It ensures non-blocking and full connectivity even when broadcast or multicast of input channels is required. It exchanges commands (incl. hardware or routing configuration) and telemetry with TMTC function as well as Reception and Transmission functions.
- Transmission function in charge of output signals Digital to Analog conversion. It includes a final stage of digital processing, the Digital to Analog Conversion stage, RF output interfaces, a reference clock interface, TMTC interface and power supplies.
- TMTC function in charge of handling TMTC interfaces with the payload as well as DTP hardware and software (boot, applicative, routing) configuration.
- Clock distribution function: distributes an external reference clock to all Reception and Transmission functions to ensure synchronization of conversions stages and corresponding digital processing.
Plan
Spaceflex DTP project plan is defined as follow :
Preliminary design conception
- DTP engineering activities: electrical architecture, mechanical definition, preliminary analysis and budgets.
- Breadboarding of elementary functions (RF functions, DCDC….)
Detailed design activities
- Detailed design and analysis of all module boards, mechanical and thermal design
- 28nm ASIC specification, architecture, design , manufacturing , tests and flight model qualification
- Test Bench development, integration and tests
- Onboard Software development, validation, integration and test
- Manufacturing, assembly and tests of a 8×8 EM DTP,
- Manufacturing, assembly and tests of a 8×8 EQM DTP,
In parallel, all standard reviews (PDR/CDR/MRR/TRR/TRB/QR) associated to product development lifecycle are covered by the project activities.
Current Status
To date, Spaceflex DTP development phase is completed. Associated key technologies (28 nm ASIC, optical links, mounting processes, thermal management…) are fully qualified.
Onboard Software is validated and qualified.
A (8 inputs x8 outputs) Qualification Model has been successful manufactured, integrated and tested to Qualification is fully integrated and currently under qualification tests.
In parallel, this VHTS DTP has already been awarded on several flight models programs where its flexible design is instantiated over 5 different configurations from 120 I/Os and 360GHz down to 28 I/Os and 72 GHz throughput. The first 2 FMs units are already delivered and the 1st launch has been successfully performed in October 2021.
