GR716B

Objectives

The primary objective of the proposed activity is to develop and test a new generation microcontroller GR716B based on the GR716A microcontroller. GR716B shall enable use of commercial off the shelf (COTS) FPGAs in critical space applications (beneficial not the least for satcom constellations), support switching power applications, enhance analogue functions, increase processing performance and support more advanced interfaces.
The secondary objective of the proposed activity is to extend existing GR716A Software Development Environment (SDE) from TRL 4 to TRL 6 for GR716B and porting of Zephyr RTOS to GR716B. The extension of the Software Development Environment includes software driver support for new functionality (BCC2), extending and optimizing the instruction simulator (TSIM3) and graphical debugger (GRMON3) support for the GR716B microcontroller.

Challenges

Ensure that the package design changes are not affecting functional or performance of existing or new functionality.
Ensure that the evaluation board design is possible to use for validation of new functionality.
Ensure no errors in the integration of new digital functions and interfaces.
Ensure no errors in the integration of new analogue functions and interfaces.
Ensure that the Analog performance are met in all process corners or over full temperature range

Benefits

The ceramic package type is easy to mount on PCB and qualified for space.
The fault tolerant design of the GR716B microcontroller in combination with the radiation tolerant technology provides radiation hardened effects for high reliability applications and monitored to support mixed-criticality applications
High electrical performance.
Defined radiation characteristics.
Existing software support.
No US content.

Features

GR716V product features

The specific features related to the CQFP package:

Specifications for the entire product:

System frequency up to 100 MHz
SpaceWire links up to 200 Mbps
Total Ionizing Dose (TID) up to 300 krad(Si)
Single-Event Latch-up Immunity (SEL) to
LETTH > 118 MeV-cm2mg
Single-Event Upset (SEU) below TBD errors per device and day in space environment

Support for single 3.3V supply

System Architecture

The figure below illustrates the architecture for the entire product.

GR716B system architecture

• Fault-tolerant SPARC V8 processor with 31 register windows, 192KiB EDAC protected tightly coupled memory and support for compressed instruction set.
• Double precision IEEE-754 floating point unit
• Memory protection units
• Non-intrusive advanced on-chip debug support unit
External EDAC protected 8-bit PROM/SRAM, SPI memory protected by EDAC and dual memory redundancy
Hardware FPGA programming and scrubbing • Real-Time Accelerators and programmable DMA
SpaceWire router with 2 external ports and time distribution
MIL-STD-1553B interface
CAN FD interface with CANOpen support
PacketWire with CRC acceleration support
Programmable PWM interface with Digital voltage control and motor control loop support
Programmable pulse-width-modulation DAC
SPI with SPI-for-Space protocol support
On-chip four channel 12-bit DAC, four 13/14-bit ADC and fast analogue comparators
10/100 Ethernet, UARTs, SPI, I2C, GPIO, Timers with Watchdog, Interrupt controller, Status registers, UART debug, etc.