PAGE CONTENTS
Objectives
The target of this development is to improve the phase noise of a fixed frequency oscillator by use of STW delay line and optimized phase/frequency locking and phase noise reduction electronics.
The activity will be based on previous work performed at Kongsberg Norspace (SAWRES) where unique performances were demonstrated, yet at low TRL level (TRL-4). The aim in this activity is, amongst others, to implement and test a complete LO Elegant Breadboard.
The most challenging requirement of the unit is the phase noise specification. The requirement induces challenging performance demands on some of the building blocks, especially the phase detector and the VCO. Also the internal OCXO needs to be focused on and a very low phase noise performance is needed.
Challenges
In the previous work performed, a VCO with state-of-the-art phase noise performance was demonstrated. Even if superior phase noise performance was shown in the previous project, additional 5-7dB improvements is needed to comply with the phase noise requirement of the complete phase locked loop local oscillator for this program. The main parameters that are further optimized are the VCO signal power, noise characteristics and the delay in the STW delay line.
Plan
The work is split in five tasks
Task 1: Literature survey and baseline design
Task 2: Design of ciritcal blocks and breadboarding
Task 3: Detailed design of EBB
Task 4: Manufacturing and test of EBB
Task 5: Conclusions and way forward
Current Status
The program is now completed.
After initial investigation and critical breadboarding, the detailed design of all building blocks were established. The optimised building blocks are fabricated, characterized and verified. Two complete VCOs and later also a complete LOs (PLL) Elegant Breadboards (EBB) were assembled and tested. Based on the reported result the TRB/Final Review was held.
