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StatusOngoing
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Status date2024-03-01
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Activity Code7B.069
The objective of this Project is to create a breadboard of an integrated wideband multiplexer, supporting both terrestrial and satellite 5G communication, to perform a first validation of the related enabling technologies.
The activity includes a first phase which foresees the study and definition of possible scenarios and use cases which benefit from the exploitation of this innovative technique.
In parallel, the Technical Specifications of the system are defined.
The Activity proceeds with the analysis of possible technologies which, after a trade-off analysis performance and complexity lead to the selection of a Technical Baseline. This represents the starting point for the system design phase, which considers both the design of a MMIC device and of a breadboard for its validation. The design is assisted by the definition of an Implementation Plan and a Validation Plan, which includes a first functional verification on the MMIC device and then a detailed verification after its installation on the breadboard.
The outputs of the validation phase allow to identify a set of technological gaps with the objective to propose possible improvements and enhancements to increase the TRL of the system in view of its possible commercialization / industrialization.
The challenging issue of this project concerns the need to optimize the RF performances of the system, in particular the insertion loss, the related passband ripple and rejection margins, while maintaining the order of the filters limited. The final solution shall guarantee an adequate level of matching both at the input and the output interface. The design shall maintain reduced the design/implementation complexity, compatibly with the realization of 3 channels of filters (low-band, mid-band and high-band) in monolithic technology.
The development of this technique represents an enabling factor in addressing the upcoming trend in satellite communications. This trend envisions the utilization of High Throughput Satellites (HTS) that exploit Frequency Division Duplexing (FDD) communication methodology.
Therefore, to adapt to upcoming trends and assure 5G satellite developments competitive, the need to adjust the architectures to the FDD communication mode arises.
In this process of technological innovation, the possibility of integrating terrestrial 5G services with space assets assumes an important relevance, providing for hybrid-type architectures and deployments, guaranteeing a strategic position of Europe in forecast of future developments.
Integrated wideband multiplexers can be incorporated into standard user terminals using 5G technology (including but not limited to smartphones, tablets, and IoT devices).
To assure the integrability to be compatible with these devices, maintaining the paradigms of compactness, reduction of the complexity, consumption, and usability by the end user in common contexts or customized to specific services, it is of significant importance to identify methodologies based on MMIC techniques (Monolithic Microwave Integrated Circuits) that can be in line with the needs previously described.
The main Activity’s features are:
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Identification of operational scenarios and use cases, identification of KPIs for technological benchmarking. State-of- the-art survey and critical assessment of the identified technological options. Definition of the Technical Specification of the system. Selection of the technological baseline.
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Design and manufacturing of the multiplexer and the demonstrator: this phase is assisted by specific analyses and simulations to optimize the theoretical performance. The design concerns both the product of the activity, i.e. the MMIC wideband multiplexer, and the breadboard necessary for its validation.
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Definition of the Validation Plan, including a set of test cases aimed at verifying compliance with the Technical Specification. Each test case is accompanied by its procedures and success criteria.
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Test campaign: the MMIC devices are installed in the Breadboard specifically developed and manufactured for the execution of the tests, which take place in a laboratory environment equipped with instrumentation suitable for performing radiofrequency tests and measuring the system performance.
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Technological evaluation of the developed devices on the basis of the performances obtained. Identification of developments to increase the TRL (technology readiness level) of the technologies developed and roadmap.
The overall system consists of 2 main sub-systems, which are integrated to handle the operations.
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MMIC wideband multiplexer, which represents the focus and the main innovative output of the Activity.
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Breadboard for testing, which is developed to allow the characterization and validation of the MMIC multiplexer during the Test Campaign, and is designed with the objective to perform RF measurements and derive the performance parameters of the multiplexer.
More in detail, the MMIC Multiplexer is in turn be composed of 3 RF channels, representing a low-band filter, a mid-band filter and a high band filter. Each channel is represented by its specific design and technology, which is determined with the objective to optimize the expected performance.
Output and Input interfaces are developed to integrate the MMIC multiplexer with the Breadboard and with the external environment (laboratory instrumentation and equipment) to perform the full validation tests.
The system architecture in represented in the high level description schematic reported in the following figure.
The project foresees the following Milestones (MS).
MS1, upon successful completion of WP2, expected by November 2023. MS2 at the end of WP4 activities, due in May 2024. Positive conclusion of WP5 activities lead to MS3, planned for December 2024. Upon the Agency’s acceptance of all deliverable items due under the Contract and the Contractor’s fulfilment of all other contractual obligations, the final Milestone MS4 is expected to be fulfilled by September 2025.
The Activity started on July 2023. The Milestone MS1 has been completed in December 2023. Team is currently performing the activities of WP3: Design of the Multiplexer and the Demonstrator
