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Objectives
The activity “Joint Turbo Decoding and Carrier Synchronisation” was carried out by Advantech Satellite Networks and its partners Turbo Concept and Eurecom.
The main objective of this project was to develop and validate new techniques that enable power efficient transmission for satellite receivers. While the algorithm investigations and their performance evaluation were not limited to any specific air interface, the main focus was on DVB-RCS and DVB-S2 compatible receivers. Due to the dominant role of conventional carrier synchronisation techniques in the receiver performance degradation, the work was directed towards improving this aspect; i.e., the frequency and phase synchronisation algorithms.
In the first part of this project, a set of algorithms, providing significant improvement in carrier synchronisation accuracy, was selected. Carrier synchronisation algorithms were developed that can take advantage of the iterative decoding process for turbo codes and LDPC codes in order to enhance the performance, especially at low coding rates and for short bursts and in the presence of severe phase noise.
In the second part, the selected algorithms were implemented and tested in hardware. The final validation included lab testing for a pre-selected set of transmission modes.
Challenges
- The impact of synchronisation on the performance of burst mode receivers operating at low coding rate;
- Investigate carrier synchronisation techniques that are robust against phase noise and carrier frequency offset;
- Trade-off between algorithm complexity and achievable performance;
- Trade-off between the hardware throughput and the achievable performance.
Plan
- Define and justify the system and channel parameters for the reference DVB-RCS system. Analyse the performance of the best known classical carrier synchronisation;
- Perform a critical literature review of the published joint turbo decoding and synchronisation algorithms;
- Select the most promising candidate schemes;
- Build simulation software to assess the performance of the selected schemes and finally compare their performance and complexity;
- VHDL design of the selected algorithms;
- Validation of the developed design in FPGA based hardware platform.
Current Status
The initial goals have been achieved and the corresponding activities completed. Extension of the work to consider burst detection and timing synchronisation is expected to start in late 2006 or early 2007.