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StatusOngoing
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Status date2024-11-11
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Activity Code5F.038
The objective of this activity is to design, simulate and test a high data rate Forward Error Correction on-board decoder and demonstrate this via a breadboard running at a data rate of at least 10 Gigabits per second (Gbps) with soft decision decoding. The decoder shall target next generation optical inter-satellite links and shall be made lightweight in terms of onboard resources usage.
Besides the breadboard-level hardware demonstration, target FEC performances at higher rates (up to 100Gbps) will be investigated and assessed.
The target TRL for this activity is 4.
The challenges to be overcome during the activity will mostly involve the design of a lightweight FEC code to work at very high datarates. Another challenge will be the implementation of the decoder on hardware platforms with comparable capabilities of the ones currently available and/or planned for satellite communication payloads, posing a limitation on the processing performances.
The main benefit of this development effort resides in the “lightweight” quality of the FEC code to be developed and implemented. This development would allow to identify FEC code qualities that enable higher datarate for on-board communication payloads, still with relatively limited resource usage. Having the possibility to demonstrate the decoding capabilities on hardware breadboard will also help to identify and assess possible limitations and bottlenecks for very high data rate (i.e. towards 100 Gbps) applications.
The communication scenarios will represent typical Optical Inter-Satellite Link (OISL) applications. Hence the channel dynamics will reproduce the one of an optical link in free-space, taking into account the link budgets for different system configurations, as well as the intensity fluctuations (mostly induced by pointing errors and micro-vibrations).
The development products will consist of software, firmware and hardware components.
As for the software, a set of FEC modelling and simulation tools will be used to design the code and assess its performances. A software-based abstraction of the intensity fluctuations in the OISL channel will be also present
The hardware implementation will include both the encoder and the breadboard decoder, though only the decoder is required and expected to process the bitstream in real time.
The expected system shall consist of a hardware-based encoder, an OISL channel model, and the breadboard decoder. Of course, the encoder and decoder implementation will depend on the FEC selection and ad-hoc design.
During design and development phase, the support of software models for the communication channel and the FEC code will also allow the consortium to assess theoretical performances and limitations of the selected solution for very high data rate applications.
The project will start with a State-of-Art assessment for potential FEC candidates and available payload processing units for communication payloads. After this phase, the design of the FEC code, and the related design of the decoder breadboard and encoder hardware will follow. In the implementation phase, the breadboard will be developed and the support hardware will be setup. The test and verification phase will assess whether the expected performance of the system have been achieved, and possible deviations will be identified and investigated. The final phase will consist of a technology evaluation and of a suggestion for development roadmap to bring the concept to higher TRLs.
The project has kicked off in September 2024.At the time of writing, the Consortium is looking into the state of the art and exploring possible solutions for FEC design and its implementations in platforms whose resources are compatible with the satellite-based payloads.
