O3KHPE - IP Core Development for CCSDS based Optical Payload Data Transmitter

  • Status
    Completed
  • Status date
    2024-12-22
  • Activity Code
    3C.021
Objectives

The main objective of the project is to develop the VHDL IP Cores implementing coding and synchronization layer for optical telemetry described in the CCSDS 142.0-P-1.1 standard. More in details, the standard describes High Photon Efficiency (HPE) and Optical On-Off Keying (O3K) optical telemetry links. The IP Cores are written in technology independent VHDL and for each configuration (HPE, O3K-RS and O3K-LDPC) a characterization on AMD KU060 was performed. Finally, validation on target FPGA technology was carried out.

Challenges

The main challenge of this project is to develop a re-usable product that has to be configurable, technology independent and fully verified in accordance with the ECSS standard and validated on a relevant HW platform.

Benefits

The resulting IP Cores will be available in ESA portfolio, this means that all member states will have access to these building blocks for the development of an optical communication system compliant with CCSDS 142.0-P-1.1. 

Features

Configurable at synthesis level for:

  • HPE

  • O3K-RS

  • O3K-LDPC

Maximum supported channel data rate: 8 Gbps for HPE, 10 Gbps for O3K.

Standard I/O and M&C interfaces based on AXI standard for smooth integration.

Fully characterized on AMD KU060 FPGA and validated on AMD KU040 FPGA.

System Architecture

The IP Core implements three different architectures supporting the three telemetry waveforms described in CCSDS 142.0-P-1.1: HPE, O3K-RS, O3K-LDPC.

These three IP Cores implement the coding and synchronization layer, in particular HPE uses a Serially Concatenated convolutionally coded Pulse Position Modulation (SCPPM) encoder, whereas O3K can support either Reed-Solomon (RS) or Low Density Parity Check (LDPC) encoders.

Plan

The project plan consists of the following phases:

  • Requirements definition.

  • Architecture definition.

  • VHDL design and verification.

  • Characterization on target technology.

  • Validation on COTS development board.

Current status

The Project is successfully closed. The IP Core VHDL database has been delivered to ESA as well as all expected deliverable documents.

The IP Core database will be part of the ESA IP Core portfolio.

Documentation

Documentation may be requested

Prime Contractor

Last update
2024-12-22 14:13