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StatusOngoing
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Activity Code5C.497P1
The main objective of this ARTES project is to develop a prototype of a high performing Q/V Band Direct Quadrature Demodulator RFIC, improving the solution footprint and power consumption compared to standard heterodyne down conversion approach.
The following main characteristics reflects the Direct Quadrature Demodulator:
- Achievable RF frequency – 47.2 to 52.4 GHz.
- Achievable demodulation (channel) bandwidth - ≥ 2 GHz.
- Conversion gain - ≥ 15 dB.
- Impairments (e.g. I&Q unbalance) < 2°.
- Receiver minimum Power Detection Level - ≥ 35 dB.
- Power consumption ≤ 1 W.
- High integration to reduce size.
The main challenges with the direct-down conversion architecture are the sensitivity to LO leakage to the RF input, causing DC-offset in the I/Q-baseband amplifier chain. Even-order distortion causing large-signal interferers at RF to be down converted to baseband, and the high gain needed in the RF and baseband paths as no amplification can be applied at an IF frequency.
One of the key performance metrics defined for the QV-band direct downconverter is good IQ balance over a large bandwidth. Hence, an architecture based on a fully complex IQ mixer is proposed. This mixer architecture has successfully been used in calibration-free mm-wave wide-band integrated transceivers by Sivers Wireless AB.
The solution target:
- Reduction in power consumption by 10%.
- Reduction of mass and volume by 50% compared to standard heterodyne down conversion approach.
Part of the technology trade-off will be the use of SiGe technology which could deliver an order of magnitude size and power consumption reduction to support above reduction targets.
The product features are:
- Q/V band support.
- Low power consumption.
- High integration level.
- Support for SPI control of device.
- Auxiliary function for debug and test.
- Bias and reference for stable operation over temperature.
The top-level block diagram of this Direct Quadrature Demodulator RFIC is outlined below:
The main blocks are RF balun and VGA, followed by a Mixer, and then a baseband circuitry handling amplitude control, amplification and DC-offset compensation.
The project is organised in the following phases:
- Study and technical specification completion.
- Design phase.
- Hardware fabrication.
- Performance validation.
- Project and results summary.
- Project closure.
The project is in design phase and will perform a (PDR) Preliminary Design Review for the schematics outline and some early simulation results.
