Reconfigurable Applications Demonstration Equipment (RADE)

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The ability to perform radio functions in the software domain enables cheaper, more reliable and highly flexible systems to be developed. This is important in the space segment, where the expected life of the equipment is long and the ability to configure and upgrade the radio to implement additional features and requirements after deployment is highly desirable. The more of the design that can be made “soft”, the greater the ability to re-use technology and capitalise on previous investment.

Using ITAR free, Mil-Aero, industrial grade, or other unrestricted components COM DEV International Systems aims to develop RADE ( Reconfigurable Applications Demonstration Equipment) a COTS based, on-orbit reconfigurable platform. 

RADE aims to develop a reconfigurable hardware platform that can be qualified and reused in the development of a variety of different applications.
The platform’s functionality and performance will be evaluated under this programme using a typical application of an AIS receiver. COM DEV International Systems will use this application to demonstrate the ability of the platform to be reconfigured and change modes of operation.
Reliability issues at early stages dramatically slow development programmes having a negative impact to the performance of the application under development leading to costs and schedule overrun.
Producing payloads based on “reusable” design concepts reduces this risk.  Being a reconfigurable hardware platform that can be qualified and reused in the development of a whole host of different applications, RADE represents a major development in this direction.
Component selection is a major issue since the system needs to be inexpensive but also needs to be able to meet the stringent requirements of a space mission.
One of the most important benefits of RADE is the ability to allow equipment developers to re-use reliable hardware to develop their applications at a very short timescale and low costs.
Another way to enable cost reduction is to design the platform with most of the technology in the ‘soft’ domain and adapt the software to meet the specific needs of the application under development.
RADE is aimed at the “MicroSpace”/small-sat segment. It is entirely export/restriction-free (e.g. non ITAR), using only Mil-Aero, industrial grade or other similarly unrestricted components. The result of these aspects of the design philosophy being that the target range of markets for this platform is greatly enhanced. RADE will be in-orbit reconfigurable allowing enhancements to the firmware to reflect ever evolving signalling standards and possibly extending mission life or usefulness as a result.
All of the above go to create an innovative, low cost, resilient platform with a short production time suitable for many markets and applications.
The RADE AIS Receiver is a Direct RF Sampling (DRFS) type with support for multiple separate and independent antenna interfaces sampled by a high performance multi-channel A/D converter clocked by a low-noise high-stability clock. For redundancy purposes, multiple RADE AIS receivers can be configured for either hot or cold redundancy. 
The RADE AIS Receiver is designed to be in-orbit reconfigurable i.e. the spacecraft’s on-board computer (OBC) can upload software (including FPGA firmware and microcontroller software) images to the equipment.
The microcontroller provides Telemetry and Tele-command (TMTC) functions, monitors the system, maintains various logs, and enables the software to be uploaded.  The application FPGA provides a platform for high speed application logic such as Digital Signal Processing. Spacecraft interfaces are provided for TMTC, payload data and power.  
The RADE AIS Receiver is part of the RADE-enabled products being planned by COM DEV International Systems for micro-space application.
A hallmark of the RADE-enabled products is the ability to seamlessly interconnect into a larger integrated network where data is routed to/from individual processing nodes and/or storage devices.
The overall project will be executed  in four phases which may operate concurrently:
Phase 1: Refinement of the architecture, mechanics, circuit design and EEE selection and procurement.
Phase 2: Manufacturing and assembly, with the major constituents being assembled and tested before integration into the unit as a whole.
Phase 3: Software development of the FPGA application and the target microcontroller.
Phase 4: Testing where the application system will be reconfigured and the top-level system tested demonstrating the satellite AIS application.
Current status
The Baseline Design Review (BDR) has been successfully held in March 2014.  During the baseline design, the product requirements were identified resulting in the definition of the system architecture, dissemination of the sub-system requirements and identification of the critical components.

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