SDRNeXT

Status

Ongoing
Status date

2025-06-24
Activity Code

5C.510

Objectives

The Small Satellites’ Software-Defined-Radio (SDR) market needs an increase in RF bandwidth and sampling frequency, in a higher number of channels and in more data processing power. This enhances even more for AI operations that requires to move to more powerful devices, using state of art FPGAs, higher component grade capability and to consider “clustering approach” for multi-channels architectures. The main objective of the SDR NeXT project is to design a software-defined reconfigurable platform using a digital board with an high-performing System on a Chip (SoC) as core.

Challenges

The SDRNeXT project targets a high-performance SDR product to penetrate the space SDR market. Herein lies a key challenge to deliver the right set of performance in the shortest possible timeframe. Time-to-market is a challenge for this complex development.

Benefits

The SDRNeXT Product is targeting the Payload market for Small Satellites, mainly for high-speed data acquisition and processing. This includes telecommunication, Earth observation products, as well as scientific and research missions.

SDRNeXT's selling point is its capacity to process a large number of channels with a larger frequency bandwidth in addition to operating synchronously, with a high-performance processing platform at its disposal.

Its modular design allows the payload to be customisable according to the customer needs in terms of operation frequency, signal bandwidth, sample rate connectors and mechanics. The product design and component selection has been made to achieve high speed and powerful data processing as well as being in-flight re-configurable.

Features

Powerful data processing Zynq UltraScale+ with latch-up protected design.
Radiation tolerant processor for boot management and supervisor watchdog.
3 x 256 Mbytes NOR flash boot memories in addition to a radiation tolerant Golden Memory of 16 Mbytes.
Mass Storage Memory (2x128 GB eMMC and 2x171 GB Nand Flash),
Four GB DDR4 SDRAM with 512 MB ECC.
Low Phase Noise reference oscillator that can be GNSS disciplined. Fully synchronous clocks for ADC and DAC. In addition to two fractional PLL for variable Local Oscillators.
Advanced design allowing reliable in-flight re-configuration.
Vin +10.8V to +33.6V Bus voltage compatible, allowing to be connected directly to battery bus voltage or behind stabilised PSU.
CubeSat, nanosat or microsat compatible.
Fully shielded and ruggedised enclosure.
Reliable product with risk acceptance of a five-year lifetime.
Analogue Front End with two (up to four) Tx channels and four (up to six) Rx channels
High-speed interface (one Gbps ethernet, SpaceWire)

System Architecture

The SDR NeXT project, as a next generation SDR platform, is built as a modular platform, comprising four sections implemented as four electronic boards, each with embedded software serving a specific purpose.

The core is a multipurpose digital section based on the high-processing power of a SoC Zynq UltraScale+. The PCB card is designed to provide mass memory storage, high processing throughput, multiple configuration memories and high-speed communication interface.

Additional communication interface is also implemented on a second card; the communication section.

On top, a flexible and modular transceiver capacity is added with multichannel synchronous receivers and transmitters to provide high RF performances; targeting up to 9 GHz RF input and up to 500 MHz of sampling bandwidth per channel. To support this, the third section is the analogue card which has the analog front-end with Digital-to-Analogue Converters (DACs) and Analog-to-Digital Converters (ADCs) and part of the receiver (Rx) and transmitter (Tx) RF Front-End (FE) chains.

Part of the Rx and Tx channels are implemented in the RF card which provide custom specific capability and a Radio Frequency (RF) front-end.

Plan

The project is targeting a breadboard phase and prototyping phase to derisk the design and to functionally validate the design. After consolidating the electronic design with updated schematics and refined mechanics, an Engineering Model is targeted to perform a functional validation.

In the second phase, the objective is to qualify the product so that it becomes ready for the market. A Qualification Model is produced and tested during this phase. Furthermore, its industrialisation plan is targeted to define manufacturing processes, workmanship verifications and acceptance testing.

Current status

The design, validation and qualification of the SDRNeXT product is currently ongoing.

The project has successfully passed the Requirements Review and the Preliminary Design Review.

Commercialisation and Go-to-Market Strategy is being developed.