TOMCAT

Status

Ongoing
Status date

2025-04-08
Activity Code

3F.033

Objectives

The objective of the project is to develop a flat panel Ka-band LEO-/NGSO-SOTM broadband User Terminal (UT) appropriate for integration into vehicles. The UT is constellation agnostic, i.e., it supports connectivity to the upcoming constellations of EU and Canadian operators. Compatible modems (e.g. 5G-NTN) will be integrated as soon as available.

Challenges

Integration density
Radio Frequency (RF) performance (RX noise figure)
Compliance to power masks

Benefits

Due to the applied architecture with an application-specific baseband processor / digital beamformer IC (ASIC), the UT has a better power efficiency than existing solutions. The architecture also avoids the use of extremely expensive Field-Programmable Gate Arrays (FPGAs) and uses cost efficient Radio-Frequency Integrated Circuits (RFICs); therefore, the manufacturing cost can be reduced significantly.

Features

Compact Frequency Division Duplex (FDD) User Terminal for Non-Geostationary Orbit (NGSO)-mobility applications, scalable architecture, i.e., different size apertures can be realised by using the same platform. The platform supports classical L-band modem interfaces as well as Digital Intermediate Frequency Interoperability (DiFi). The UT can be integrated in any type of vehicle.

System Architecture

The UT antenna uses active phased- array technology with separate apertures for RX & TX, for FDD transmission / reception. The architecture relies on hybrid beamforming with distributed base band processing / digital beam forming using an application- specific type of IC (DDBB). The RF-unit consists of a stacked patch array antenna and one RF-Frontend / analogue beamformer IC per 4 antenna elements. The RF-IC integrates an up-/downconverter. The connection between RF-IC and DDBB is therefore on a low IF or even Zero-IF (selectable). The DDBB serves 4 RF-ICs, so 16 antenna patches are controlled by one DDBB with integrated ADCs and DACs. On the digital side, the DDBBs ICs are connected with a high- speed SERDES link in daisy chain fashion. All chains are connected to a central signal combination logic that syncs up the signals, before sending the combined signal to the modem.

Plan

In the project, two revisions of the terminal prototypes (Prototype V1, and Prototype V2) will be built up and delivered. The development of each prototype revision consists of a development phase and an integration phase. After each development phase and each integration phase, a milestone is planned.

Current status

Currently, the printed circuit boards (digital mother board, RX panel) of the terminal prototype V1 are in production, the TX panel is in design. The software and the FPGA design that will run on the terminal prototype V1 are prepared on several evaluation boards, to have a tested environment for the integration.

After production and assembly of the boards, the software and FPGA will be integrated to the target system.

The test and integration of the terminal prototype V1 is planned in several steps: bring-up of the digital mother board standalone, then connecting the RX-panel, and, finally, adding the TX panel. A measurement campaign in the compact test range ends the integration phase.