VOCS | ESA CSC

Space Segment - Payload

Status

Completed
Status date

2024-09-18
Activity Code

5C.441

Objectives

The main objective of the VOCS proposal is to design, develop, breadboard and test all the subsystems of a VDE-SAT compliant payload for small platforms such as cubesats and microsatellites. Critical breadboarding is carried out to achieve a significant reduction of DC power consumption, mass and overall volume.

Moreover, the project focuses also on the design, implementation and test of the On-Board Data Processing (OBDP) modules, related to a VDE-SAT payload.

Challenges

The major critical area of the activity is the implementation and the breadboarding, facing challenging technical issues and technology gaps.

The main technology gaps to bridge are:

compact and light VHF duplexer and power consumption of the PA needed to close the down-link budget with 3 VDE carriers with high duty-cycle, in case of half duplex mode for cubesats
design of RAS Filter(s) in order to be compliant with RAS normative

Benefits

World-wide VDE-SAT missions meaning that the duty-cycle should be as high as needed to provide VDES services over all the Earth area covered by sea;
VDES service can be activated even with few satellites (e.g. >=1) able to store and forward data using even few ground stations (e.g. >=1).
The implementation of the On-Board Data Processing (OBDP) makes large reuse of existing C++ software developed for ground applications ported on the general purpose ARM processor available on the selected payload On-Board Computer

Features

The main outcome of the project is a VDES payload(s) (half duplex and full duplex solution) that integrates a VHF RF front-end compliant with the main VDES regulations.

The product is planned to be used with:

LEO satellites deployed using SSO at an altitude of 600 km
Regenerative satellite to allow the initial deployment of the VDES network with limited investments

Moreover, one of key elements of the proposal is the possibility of reusing the software architecture adopted by MBI ground E-SSA receiver where successive interference cancellation (SIC) technique is used to maximize the performances in presence of multi-access interference (MAI). The solution hence includes an enhancement of the already used E-SSA protocol and the Consortium can exploit the availability of an operational E-SSA-based Testbed which embeds an E-SSA Demodulator.

System Architecture

Two main architectures are envisaged: a lighter VDE-SAT payload adopting just one down-link carrier embarked on a small half-duplex Cubesat (VOCS1) on one hand, with a reduced duty-cycle to meet power budget. On the other hand, an enhanced VDE-SAT payload fully exploiting VDE-SAT with more performing antennas embarked on full-duplex small Microsatellites (VOCS2).
A third solution (VOCS-3), a full duplex solution which foresees the integration of TX and RX chain(s) on two different small satellite platforms, each of them acting as ONLY-TX or ONLY-RX, is under analysis.

The VOCS satellite architecture is based on the following key sub-components:

Circular-polarization TX/RX VHF antenna, Yagi for VOCS2 and cross-dipole for VOCS1
VDE-SAT Transceiver containing:
- Satellite RF front-end (SAT-FE) composed of all the analogic stages needed to manage the VHF signal between the antenna and the SDR board such as diplexer (only VOCS2), power amplifier(s), Low Noise Amplifier(s) and VHF filters
- SDR board which includes the ADCs and DACs required to perform digital to analogic and vice versa conversions as well as some RF stages such as analogic up-conversion and amplifications
Payload On-Board Computer (pOBC), including a Programmable Logic (PL) and an Application Processing Unit (APU)

Plan

The project plan foresees a unique phase which includes the following milestones after the KO meeting (T0):