Description
The objective of this activity is to develop and evaluate efficient digital beamforming algorithms and architectures for payloads utilising digital processors. The developed concepts shall be implemented and tested on a representative digital processor testbed to demonstrate the power consumption improvement.
Targeted Improvements: Reduction of power consumption by 50% with respect to current digital beamforming implementation. Reduction by 50% of the number of ASICs.
Description:
Current and future very high throughput payloads need to simultaneously generate hundreds to thousands of beams over the coverage area, requiring a very large aggregated capacity (in the order of a few THz) to be beam-formed. Digital beamforming of such a large aggregated capacity is currently not possible due to the limited power available on-board and to thermal management challenges. Hence, current processors are only able to perform digital beamforming on a small portion of the total system capacity.
Reduction of digital beamforming power consumption would allow the implementation of a full digital payload, resulting in many operational benefits and flexible capacity allocation, serving different users and applications. This activity will develop low-complexity, highly efficient algorithms, processing techniques and architectures to significantly reduce power consumption, mass and volume and improve integration efficiency. Mathematical techniques combined with spatial symmetry of beams and spatial symmetry of radiating elements will be exploited to reduce the processing to a simple set of additions/subtractions, in many cases fully avoiding multiplication operations. A representative processor testbed will be developed and used to implement and test the developed algorithms and processing techniques.