Description
The objective of this activity is to design, develop, manufacture and test analogue-to-digital and digital-to-analogue converter Intellectual Property (IP) for ultra-deep sub-micron technology, compatible with system-on-chip implementation in space andground applications.
Targeted Improvements: Enabling a European source of analogue-to-digital and digital-to-analogue converters, minimising the chip area with a sampling speed of at least 8 GS/s and a power consumption of less than 200 mW.
Description:
The new generation of low cost, highly integrated baseband systems on chip (SoC) for satellite communications (for example regenerative payloads, digital beamforming networks) require high-speed and very low power analogue-to-digital and digital-to-analogue converters (ADCs/DACs). Currently there is no European or Canadian solution providing IP for high-speed ADCs/DACs with a sampling rate of at least 8 GS/s and a power consumption below 200 mW.
In order to reduce the European and Canadian dependence on such critical building blocks,the development of enabling IP for a new source of ADCs and DACs is required. Various foundry processes shall be assessed. Based on the most recent market trends, one reference scenario shall be selected for developing the ADC and DAC IP. The electrical performance of the developed IP shall be demonstrated with prototypes that shall be designed, developed, manufactured and tested.
Procurement Policy: C2: Activities are in open competition, where a significant participation of non-LSIs is requested. For additional information please go to EMITS news "Industrial Policy measures for non-primes, SMEs and RD entities in ESA programmes".
Footnote: On Delegation Request activities will only be initiated on the explicit request of at least one National Delegation.